Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) CSPBGA 74

REV. B

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AD5516

16-Channel, 12-Bit Voltage-Output DAC

with 14-Bit Increment Mode

*Protected by U.S. Patent No.

FEATURES

High Integration:

16-Channel DAC in 12 mm ⴛ 12 mm

CSPBGA

14-Bit Resolution via Increment/Decrement Mode

Guaranteed Monotonic

Low Power, SPI

, QSPI™, MICROWIRE™, and

DSP Compatible

3-Wire Serial Interface

Output Impedance 0.5 ⍀

Output Voltage Range

ⴞ2.5 V (AD5516-1)

ⴞ5 V (AD5516-2)

ⴞ10 V (AD5516-3)

Asynchronous Reset Facility (via RESET Pin)

Asynchronous Power-Down Facility (via PD Pin)

Daisy-Chain Mode

Temperature Range: –40ⴗC to +85ⴗC

APPLICATIONS

Level Setting

Instrumentation

Automatic Test Equipment

Optical Networks

Industrial Control Systems

Data Acquisition

Low Cost I/O

FUNCTIONAL BLOCK DIAGRAM

RESET

BUSY

DACGND

AGND

DGND

DCEN

AD5516

OUT

OFFS

DAC

BIAS

OFFS

DAC

OFFS

DAC

OFFS

DAC

REF_IN

POWER-DOWN

LOGIC

SCLK D

OUT

SYNC

INTERFACE

CONTROL

LOGIC

7-BIT BUS

ANALOG

CALIBRATION

LOOP

12-BIT BUS

MODE1

MODE2

GENERAL DESCRIPTION

The AD5516 is a 16-channel, 12-bit voltage-output DAC. The

selected DAC register is written to via the 3-wire serial inter-

face. DAC selection is accomplished via address bits A3–A0.

14-bit resolution can be achieved by fine adjustment in Incre-

ment/Decrement Mode (Mode 2). The serial interface operates

at clock rates up to 20 MHz and is compatible with standard

SPI, MICROWIRE, and DSP interface standards. The output

voltage range is fixed at ±2.5 V (AD5516-1), ±5 V (AD5516-2),

and ± 10 V (AD5516-3). Access to the feedback resistor in each

channel is provided via the R

0 to R

15 pins.

The device is operated with AV

= 5 V ± 5%, DV

= 2.7 V

to 5.25 V, V

= –4.75 V to –12 V, and V

= +4.75 V to +12 V,

and requires a stable 3 V reference on REF_IN.

PRODUCT HIGHLIGHTS

1. Sixteen 12-bit DACs in one package, guaranteed monotonic.

2. Available in a 74-lead CSPBGA package with a body size of

12 mm ⫻ 12 mm.

5,969,657.

Summary of content (16 pages)

PAGE 1
6-Channel, 12-Bit Voltage-Output DAC with 14-Bit Increment Mode AD5516* FEATURES High Integration: 16-Channel DAC in 12 mm ⴛ 12 mm CSPBGA 14-Bit Resolution via Increment/Decrement Mode Guaranteed Monotonic Low Power, SPI®, QSPI™, MICROWIRE™, and DSP Compatible 3-Wire Serial Interface Output Impedance 0.5 ⍀ Output Voltage Range ⴞ2.
PAGE 2
AD5516–SPECIFICATIONS (VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DACGND = 0 V; REF_IN = 3 V; All outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted.) Parameter1 A Version2 Unit DAC DC PERFORMANCE Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Increment/Decrement Step-Size Bipolar Zero Error Positive Full-Scale Error Negative Full-Scale Error 12 ±2 –1/+1.3 ± 0.
PAGE 3
AD5516 AC CHARACTERISTICS (VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DACGND = 0 V; REF IN = 3 V. All outputs unloaded. All specifications TMIN to TMAX, unless otherwise noted.) Parameter1, 2 A Version3 Unit 32 32 36 ␮s max ␮s max ␮s max 2.5 3.35 7 0.
PAGE 4
AD5516 TIMING DIAGRAMS SCLK 1 2 17 t3 t2 18 t1 t6 t7 SYNC t9 MODE2 t4 t5 MSB DIN LSB BIT 17 BIT 0 t8 MODE1 BUSY t12 RESET Figure 1. Serial Interface Timing Diagram SCLK t3 t7 MODE2 t2 t1 t10 t6 SYNC t4 MSB DIN t5 LSB BIT 17 BIT 0 BIT 17 INPUT WORD FOR DEVICE N BIT 0 INPUT WORD FOR DEVICE N+1 t11 DOUT BIT 17 t8 MODE1 UNDEFINED BIT 0 INPUT WORD FOR DEVICE N BUSY Figure 2. Daisy-Chaining Timing Diagram 200␮A TO OUTPUT PIN IOL 1.6V CL 50pF 200␮A IOH Figure 3.
PAGE 5
AD5516 ABSOLUTE MAXIMUM RATINGS 1, 2 Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ MAX) . . . . . . . . . . . . . . . . . . . 150°C 74-Lead CSPBGA Package, ␪JA Thermal Impedance . . . 41°C/W Reflow Soldering Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec (TA = 25°C, unless otherwise noted.) VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 6
AD5516 PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 A A B B C C D D E E TOP VIEW F F G G H H J J K L K L 1 2 3 4 5 6 7 8 9 10 11 74-LEAD CSPBGA BALL CONFIGURATION CSPBGA Ball Number Name CSPBGA Number Ball Name CSPBGA Ball Number Name CSPBGA Number Ball Name CSPBGA Number Ball Name A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C6 C10 C11 D1 D2 D10 DGND DGND NC NC SCLK NC REF_IN VOUT0 DACGND NC AVCC1 NC RFB0 DACGND AVCC2 D11 E1 E2 E10 E11 F1 F2 F10
PAGE 7
AD5516 PIN FUNCTION DESCRIPTIONS (continued) Mnemonic Function SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock speeds up to 20 MHz. Serial Data Input. Data must be valid on the falling edge of SCLK. Serial Data Output. DOUT can be used for daisy-chaining a number of devices together or for reading back the data in the shift register for diagnostic purposes.
PAGE 8
AD5516–Typical Performance Characteristics 1.0 1.0 2.0 REF_IN = 3V 0.8 TA = 25ⴗC REF_IN = 3V 0.8 TA = 25ⴗC 1.5 0.6 0.6 0.4 0.4 REF_IN = 3V 0.2 0 –0.2 –0.4 ERROR (LSB) INL ERROR (LSB) DNL ERROR (LSB) 1.0 0.2 0 –0.2 INL 0.5 +VE DNL 0 –0.5 –VE DNL –0.4 –1.0 –0.6 –0.6 –0.8 –0.8 –1.5 –1.0 –1.0 –2.0 –40 0 1000 2000 3000 DAC CODE 4000 0 1000 4000 3 0.006 0.004 –1 VOUT (V) VOUT (V) 0 0 –0.006 –0.002 0 20 40 0.0 –0.004 POSITIVE FS ERROR –20 0.002 MIDSCALE –0.
PAGE 9
AD5516 450 40 40 REF_IN = 3V TA = 25ⴗC 400 REF_IN = 3V TA = 25ⴗC 300 250 200 150 FREQUENCY (%) FREQUENCY (%) FREQUENCY 350 20 20 100 50 0 –10 0 2.4893 2.4896 VOUT (V) 2.4899 TPC 10. AD5516–1 VOUT Repeatability; Programming the Same Code Multiple Times 0 LSBs 0 –10 10 TPC 11. Bipolar Error Distribution 30 6 REF_IN = 3V TA = 25ⴗC ERROR (LSB) ERROR (LSB) FREQUENCY (%) REF_IN = 3V T A = 25ⴗC 5 2.0 10 10 TPC 12. Positive Full-Scale Error Distribution 2.
PAGE 10
AD5516 FUNCTIONAL DESCRIPTION The AD5516 consists of sixteen 12-bit DACs in a single package. A single reference input pin (REF_IN) is used to provide a 3 V reference for all 16 DACs. To update a DAC’s output voltage, the required DAC is addressed via the 3-wire serial interface. Once the serial write is complete, the selected DAC converts the code into an output voltage. The output amplifiers translate the DAC output range to give the appropriate voltage range (± 2.
PAGE 11
AD5516 SYNC must be taken high and low again for further serial data transfer. SYNC may be taken high after the falling edge of the 18th SCLK pulse, observing the minimum SCLK falling edge to SYNC rising edge time, t6. If SYNC is taken high before the 18th falling edge of SCLK, the data transfer will be aborted and the addressed DAC will not be updated. See the timing diagram in Figure 1.
PAGE 12
AD5516 A data transfer is initiated by writing a word to the TX Register after the SPORT has been enabled. In write sequences, data is clocked out on each rising edge of the DSP’s serial clock and clocked into the AD5516 on the falling edge of its SCLK.
PAGE 13
AD5516 APPLICATION CIRCUITS The AD5516 is suited for use in many applications, such as level setting, optical, industrial systems, and automatic test applications. In level setting and servo applications where a fine-tune adjust is required, the Mode 2 function increases resolution. The following figures show the AD5516 used in some potential applications. so that the DAC output has enough headroom to drive the BJT ~ 0.7 V above the maximum output voltage.
PAGE 14
AD5516 OUTLINE DIMENSIONS 74-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-74) Dimensions shown in millimeters A1 CORNER INDEX AREA 12.00 BSC SQ 11 10 9 8 7 6 5 4 3 2 1 A1 TOP VIEW 1.00 BSC BOT TOM VIEW A B C D E F G H J K L 10.00 BSC SQ 1.00 BSC 1.70 MAX DETAIL A DETAIL A 0.30 MIN 0.20 MAX COPLANARITY 0.70 SEATING 0.60 PLANE 0.50 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-192ABD-1 –14– REV.
PAGE 15
AD5516 Revision History Location Page 8/03—Data Sheet changed from REV. A to REV. B. Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to TPC 14 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Addition of TPC 15 . . . . . . . . . . . . . . . . . . . .
PAGE 16
–16– C02792–0–8/03(B)