Datasheet

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12-Bit, High Voltage DAC

with SPI Interface

Data Sheet

AD5501

Rev. C Document Feedback

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FEATURES

Single-channel high voltage DAC

12-bit resolution

Pin-selectable 30 V or 60 V output range

Integrated precision reference

Low power serial interface with readback capability

Integrated temperature sensor alarm function

Power-on reset

Wide operating temperature range: −40°C to +105°C

APPLICATIONS

Programmable voltage sources

High voltage LED drivers

Receiver bias in optical communications

GENERAL DESCRIPTION

The AD5501 is a single-channel, 12-bit, serial input, digital-to-

analog converter (DAC) with an on-chip high voltage output

amplifier and an integrated precision reference. The DAC output

voltage range is programmable via the range select pin (

R_SEL

is held high, the DAC output range is 0 V to 30 V. If

R_SEL

is held low, the DAC output range is 0 V to 60 V. The on

chip output amplifier allows an output swing within the range

of AGND + 0.5 V to V

− 0.5 V.

The AD5501 has a high speed serial interface, which is compatible

with SPI®-, QSPI™-, MICROWIRE™-, and DSP-interface standards

and can handle clock speeds of up to 16.667 MHz.

FUNCTIONAL BLOCK DIAGRAM

POWER-ON

RESET

DAC

INPUT

CONTROL

LOGIC

SYNC

CLR

R_SEL DGND

LOGIC

AGND

SCLK

SDI

SDO

OUT

LDAC

ALARM

POWER-DOWN

CONTROL LOGIC

PRECISION

REFERENCE

TEMPERATURE

SENSOR

12-BIT

DAC

REF(+)

–

OUTPUT

BUFFER

122.36kΩ

1713kΩ

RESISTOR

NETWORK

AD5501

07992-001

Figure 1.

Summary of content (20 pages)

PAGE 1
2-Bit, High Voltage DAC with SPI Interface AD5501 Data Sheet FEATURES GENERAL DESCRIPTION Single-channel high voltage DAC 12-bit resolution Pin-selectable 30 V or 60 V output range Integrated precision reference Low power serial interface with readback capability Integrated temperature sensor alarm function Power-on reset Wide operating temperature range: −40°C to +105°C The AD5501 is a single-channel, 12-bit, serial input, digital-toanalog converter (DAC) with an on-chip high voltage output amplifier
PAGE 2
AD5501 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power-Down Mode .................................................................... 13 Applications ....................................................................................... 1 DAC Channel Architecture....................................................... 13 General Description ......................................................................
PAGE 3
Data Sheet AD5501 The serial interface offers the user the capability of both writing to, and reading from, most internal registers. To reduce power consumption at power up, only the digital section of the AD5501 is powered up initially. This gives the user the ability to program the DAC registers to the required value while typically consuming only 30 μA of supply current.
PAGE 4
AD5501 Data Sheet SPECIFICATIONS VDD = 10 V to 62 V; VLOGIC = 2.3 V to 5.5 V; RL = 60 kΩ; CL = 200 pF; −40°C < TA < +105°C, unless otherwise noted. Table 2.
PAGE 5
Data Sheet AD5501 Typ 1 Max Unit IQUIESCENT 0.6 62 5.5 0.75 V V mA ILOGIC 0.4 2 µA Static conditions; DAC output = midscale VIH = VLOGIC; VIL = DGND dB dB DAC output = full scale DAC output = full scale µA °C TJ = TA + PTOTAL × θJA Parameter POWER SUPPLIES VDD VLOGIC Quiescent Supply Current Symbol Logic Supply Current DC PSRR4 30 V mode 60 V mode POWER-DOWN MODE Supply Current Software Power-Down Mode Junction Temperature6 Min 10 2.
PAGE 6
AD5501 Data Sheet TIMING CHARACTERISTICS VDD = 30 V, VLOGIC = 2.3 V to 5.5 V, and −40°C < TA < +105°C, all specifications TMIN to TMAX, unless otherwise noted. Table 4.
PAGE 7
Data Sheet AD5501 t4 t1 SCLK t8 t2 t3 t7 SYNC t5 SDI t6 D0 R/W t9 LDAC1 t10 LDAC2 t11 CLR t13 ALARM3 t12 VOUT 07994-003 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE. 3IN THE EVENT OF OVERTEMPERATURE CONDITION. Figure 3. Write Timing Diagram t14 SCLK SYNC R/W A2 A1 A0 X X X X X D11 D10 X t16 t15 SDO X D9 D8 Figure 4. Read Timing Diagram Rev.
PAGE 8
AD5501 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 5. Parameter VDD to AGND VLOGIC to DGND VOUT to AGND Digital Input to DGND SDO Output to DGND AGND to DGND Maximum Junction Temperature (TJ Maximum) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Range Rating −0.3 V to +64 V −0.3 V to +7 V −0.3 V to VDD + 0.3 V −0.3 V to VLOGIC + 0.3 V −0.3 V to VLOGIC + 0.3 V −0.3 V to +0.
PAGE 9
Data Sheet AD5501 CLR 1 16 VLOGIC 2 15 ALARM SYNC SCLK 3 AD5501 14 VDD SDI TOP VIEW (Not to Scale) 13 R_SEL SDO 5 12 VOUT DGND 6 11 VFB AGND 7 10 NC LDAC 8 9 NC 4 NC = NO CONNECT 07992-005 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 7. Pin Function Descriptions Pin No.
PAGE 10
AD5501 Data Sheet 0.8 45.0025 0.4 45.0000 VOUT (V) 0 44.9975 –0.4 44.9950 1008 2048 3056 4064 CODE 44.9925 07992-006 –0.8 32 0 0.05 0.10 0.15 07992-009 INL (LSB) TYPICAL PERFORMANCE CHARACTERISTICS 0.20 TIME (ms) Figure 6. Typical INL Figure 9. Output Settling Time (Low to High) 0.50 200 VDD = 62V VOUT = 30V 0 –0.50 32 1008 2048 3056 4064 CODE 0 –100 –200 07992-007 –0.25 100 0 2.5 5.0 7.5 10.0 TIME (Seconds) 07992-010 OUTPUT VOLTAGE (µV) DNL (LSB) 0.
PAGE 11
Data Sheet AD5501 12 2 10 0 AMPLITUDE (LSB) –4 –6 6 4 2 0 –8 –10 0 5 10 TIME (ms) 15 Figure 12. Digital-to-Analog Negative Glitch Impulse –4 0 5 10 TIME (ms) Figure 13. Digital-to-Analog Positive Glitch Impulse Rev.
PAGE 12
AD5501 Data Sheet TERMINOLOGY Relative Accuracy (Integral Nonlinearity) For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation in LSBs from a straight line passing through the endpoints of the DAC transfer function. Gain Error Differential Nonlinearity Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
PAGE 13
Data Sheet AD5501 THEORY OF OPERATION POWER-DOWN MODE The DAC channel can be powered up or powered down by programming Bit C2 in the control register (see Table 10). When the DAC channel is powered down, the associated analog circuitry turns off to reduce power consumption. The digital section of the AD5501 remains powered up. The output of the DAC amplifier can be three-stated or connected to AGND via an internal 20 kΩ resistor, depending on the state of Bit C6 in the control register.
PAGE 14
AD5501 Data Sheet SELECTING THE OUTPUT RANGE TEMPERATURE SENSOR The output range of the DAC is selected by the R_SEL pin. When the R_SEL pin is connected to a Logic 1, the DAC output voltage can be set between 0 V and 30 V. When the R_SEL pin is connected to a Logic 0, the DAC output voltage can be set between 0 V and 60 V. The state of R_SEL can be changed any time when the serial interface is not being used, that is, not during a read or write operation.
PAGE 15
Data Sheet AD5501 SERIAL INTERFACE The AD5501 has a serial interface (SYNC, SCLK, SDI, and SDO), which is compatible with SPI standards, as well as with most DSPs. The AD5501 allows writing of data, via the serial interface, to the input and control registers. The DAC register is not directly writeable or readable. The input shift register is 16 bits wide (see Table 8). The 16-bit word consists of one read/write (R/W) control bit, followed by three address bits and 12 DAC data bits.
PAGE 16
AD5501 Data Sheet Table 10. Control Register Functions Bit Map DB15 R/W 1 DB14 1 DB13 1 DB12 1 DB11 0 DB10 0 DB9 0 DB8 0 DB7 0 DB6 C6 DB5 C5 DB4 C4 DB3 C3 DB2 C2 DB0 1 C0 DB1 C1 Read only bit. This bit should be 0 when writing to the control register Table 11. Control Register Function Bit Descriptions Bit Name C0 DB1 DB2 C1 C2 DB[3:5] DB6 C3 to C5 C6 Description C0 = 0: the device is not in thermal shutdown mode. C0 = 1: the thermal shutdown mode is activated. C1 = 0: reserved.
PAGE 17
Data Sheet AD5501 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 20.
PAGE 18
AD5501 Data Sheet NOTES Rev.
PAGE 19
Data Sheet AD5501 NOTES Rev.