Datasheet

Data Sheet AD5450/AD5451/AD5452/AD5453
Rev. G | Page 7 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04587-003
AD5450/
AD5451/
AD5452/
AD5453
R
FB
1
V
REF
2
V
DD
3
SYNC
4
I
OUT
1
GND
SCLK
SDIN
8
7
6
5
Figure 3. 8-Lead TSOT Pin Configuration
04587-004
AD5452/
AD5453
I
OUT
1
1
GND
2
SCLK
3
SDIN
4
R
FB
V
REF
V
DD
SYNC
8
7
6
5
Figure 4. 8-Lead MSOP Pin Configuration
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND.
TOP VIEW
(Not to Scale)
AD5453
3SCLK
4SDIN
1I
OUT
1
2GND
6 V
DD
5 SYNC
8 R
FB
7 V
REF
04587-205
Figure 5. 8-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No
1
TSOT MSOP LFCSP Mnemonic Description
1 8 8 R
FB
DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external
amplifier output.
2
7
7
V
REF
DAC Reference Voltage Input.
3 6 6 V
DD
Positive Power Supply Input. These parts can operate from a supply of 2.5 V to 5.5 V.
4 5 5
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. Data is
loaded to the shift register upon the active edge of the following clocks.
5 4 4 SDIN Serial Data Input. Data is clocked into the 16-bit input register upon the active edge of the serial
clock input. By default, in power-up mode data is clocked into the shift register upon the falling
edge of SCLK. The control bits allow the user to change the active edge to a rising edge.
6 3 3 SCLK Serial Clock Input. By default, data is clocked into the input shift register upon the falling edge
of the serial clock input. Alternatively, by means of the serial control bits, the device can be
configured such that data is clocked into the shift register upon the rising edge of SCLK.
7
2
2
GND
Ground Pin.
8 1 1 I
OUT
1 DAC Current Output.
N/A N/A EPAD EPAD Exposed pad must be connected to ground.
1
N/A = not applicable.