Datasheet

Data Sheet AD5450/AD5451/AD5452/AD5453
Rev. G | Page 5 of 28
TIMING CHARACTERISTICS
All input signals are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. V
DD
= 2.5 V to 5.5 V,
V
REF
= 10 V, temperature range for Y version: −40°C to +125°C. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1
V
DD
= 2.5 V to 5.5 V Unit Description
f
SCLK
50 MHz max Maximum clock frequency
t
1
20 ns min SCLK cycle time
t
2
8 ns min SCLK high time
t
3
8 ns min SCLK low time
t
4
8
ns min
SYNC
falling edge to SCLK active edge setup time
t
5
5 ns min Data setup time
t
6
4.5 ns min Data hold time
t
7
5 ns min
SYNC
rising edge to SCLK active edge
t
8
30 ns min Minimum
SYNC
high time
Update Rate 2.7 MSPS Consists of cycle time,
SYNC
high time, data setup, and
output voltage settling time
1
Guaranteed by design and characterization, not subject to production test.
04587-002
SCLK
SYNC
DIN
DB15 DB0
t
7
t
3
t
2
t
6
t
5
t
4
t
8
t
1
Figure 2. Timing Diagram