Datasheet

Data Sheet AD5450/AD5451/AD5452/AD5453
Rev. G | Page 21 of 28
SERIAL INTERFACE
The AD5450/AD5451/AD5452/AD5453 have an easy-to-use
3-wire interface that is compatible with SPI, QSPI, MICROWIRE,
and most DSP interface standards. Data is written to the device in
16-bit words. This 16-bit word consists of two control bits and 8,
10, 12, or 14 data bits, as shown in Figure 50, Figure 51, Figure 52,
and Figure 53. The AD5453 uses all 14 bits of DAC data, the
AD5452 uses 12 bits and ignores the two LSBs, the AD5451 uses
10 bits and ignores the four LSBs, and the AD5450 uses 8 bits
and ignores the six LSBs.
DAC Control Bits C1, C0
Control Bits C1 and C0 allow the user to load and update the
new DAC code and to change the active clock edge. By default,
the shift register clocks data upon the falling edge; this can be
changed via the control bits. If changed, the DAC core is
inoperative until the next data frame, and a power recycle is
required to return it to active on the falling edge. A power cycle
resets the core to default condition. On-chip power-on reset
circuitry ensures that the device powers on with zero scale
loaded to the DAC register and I
OUT
line.
Table 10. DAC Control Bits
C1 C0 Function Implemented
0 0 Load and update (power-on default)
0 1 Reserved
1 0 Reserved
1 1 Clock data to shift register upon rising edge
SYNC
Function
SYNC
is an edge-triggered input that acts as a frame-
synchronization signal and chip enable. Data can only be
transferred to the device while
SYNC
is low. To start the serial
data transfer,
SYNC
should be taken low, observing the
minimum
SYNC
falling to SCLK falling edge setup time, t
4
. To
minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
upon the falling edge of
SYNC
. The SCLK and SDIN input
buffers are powered down upon the rising edge of
SYNC
.
After the falling edge of the 16
th
SCLK pulse, bring
SYNC
high
to transfer data from the input shift register to the DAC register.
The serial interface to the AD5450 uses a 16-bit shift register.
Take care to avoid incomplete data sequences as these will be
latched to update the DAC output.
For example,
• Loading 0x3FFF (a complete data sequence) will update
the output to 10 V (full scale).
• User intends to write 0x3200 but after 12 active edges
SYNC
goes high (incomplete write sequence). This will
actually update the following code: 0xF200.
• The user expects an output of 5.6 V. However, if
SYNC
goes high after 12 valid clock edges then an incomplete
data sequence of 12 bits is loaded. To complete the shift
register the 4 LSBs from the previous sequence are taken
and used as the 4 MSBs missing. The addition of these
4 bits will put the part in rising edge mode and the output
will show no change. Figure 54, Figure 55, and Table 11
show the data frames for this example.
Also note that if more then 16-bits are loaded to the part before
SYNC
goes high the last 16-bits will be latched.
04587-005
DB0 (LSB)
DB15 (MSB)
C1 C0
XXXXXX
DB7 DB6 DB5 DB4 DB3 DB2 DB0DB1
CONTROL BITS
DATA BITS
Figure 50. AD5450 8-Bit Input Shift Register Contents
04587-006
DB0 (LSB)
DB15 (MSB)
DB5 DB4 DB3 DB2 DB0DB1C1 C0 DB7 DB6DB8DB9
XXXX
CONTROL BITS
DATA BITS
Figure 51. AD5451 10-Bit Input Shift Register Contents
04587-007
DB0 (LSB)
DB15 (MSB)
DB7 DB6 DB5 DB4
DB3 DB2
DB0
DB1
C1 C0
DB11 DB10
DB8
DB9
X
X
CONTROL BITS
DATA BITS
Figure 52. AD5452 12-Bit Input Shift Register Contents
04587-008
DB0 (LSB)
DB15 (MSB)
DB9 DB8 DB7 DB6
DB5 DB4
DB2
DB3
C1 C0
DB13 DB12
DB10
DB11
DB0
DB1
CONTROL BITS
DATA BITS
Figure 53. AD5453 14-Bit Input Shift Register Contents
04587-054
1 1 1 1
1 1
1
1
0 0
1 1
1
1
1
1
CONTROL BITS
DATA BITS
Figure 54. AD5453 First Write, Complete Data Sequence (0x3FFF)