Datasheet

AD5450/AD5451/AD5452/AD5453 Data Sheet
Rev. G | Page 18 of 28
Stability
In the I-to-V configuration, the I
OUT
of the DAC and the
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited gain bandwidth
product (GBP) and there is excessive parasitic capacitance at the
inverting node. This parasitic capacitance introduces a pole into
the open-loop response, which can cause ringing or instability
in the closed-loop applications circuit.
An optional compensation capacitor, C1, can be added in parallel
with R
FB
for stability, as shown in Figure 44 and Figure 45. Too
small a value of C1 can produce ringing at the output, and too
large a value can adversely affect the settling time. C1 should be
found empirically, but 1 pF to 2 pF is generally adequate for the
compensation.
SINGLE-SUPPLY APPLICATIONS
Voltage-Switching Mode
Figure 46 shows these DACs operating in the voltage-switching
mode. The reference voltage, V
IN
, is applied to the I
OUT
1 pin, and
the output voltage is available at the V
REF
terminal. In this
configuration, a positive reference voltage results in a positive
output voltage, making single-supply operation possible. The
output from the DAC is voltage at a constant impedance (the
DAC ladder resistance); therefore, an op amp is necessary to
buffer the output voltage. The reference input no longer sees
constant input impedance, but one that varies with code;
therefore, the voltage input should be driven from a low
impedance source.
04587-011
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
R
FB
V
IN
I
OUT
1 V
REF
GND
V
DD
V
DD
V
OUT
R1 R2
Figure 46. Single-Supply Voltage-Switching Mode
It is important to note that with this configuration V
IN
is limited
to low voltages because the switches in the DAC ladder do not
have the same source-drain drive voltage. As a result, their on
resistance differs, which degrades the integral linearity of the
DAC. Also, V
IN
must not go negative by more than 0.3 V, or an
internal diode turns on, causing the device to exceed the
maximum ratings. In this type of application, the full range of
multiplying capability of the DAC is lost.
Positive Output Voltage
The output voltage polarity is opposite to the V
REF
polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier
because of the resistors’ tolerance errors. To generate a negative
reference, the reference can be level-shifted by an op amp such
that the V
OUT
and GND pins of the reference become the virtual
ground and −2.5 V, respectively, as shown in Figure 47.
04587-012
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
R
FB
I
OUT
1
GND
–5V
+5V
ADR03
GND
V
OUT
V
IN
V
REF
–2.5V
V
DD
V
DD
= +5V
C1
V
OUT
= 0V TO +2.5V
Figure 47. Positive Output Voltage with Minimum Components
ADDING GAIN
In applications in which the output voltage is required to be
greater than V
IN
, gain can be added with an additional external
amplifier, or it can be achieved in a single stage. It is important
to consider the effect of the temperature coefficients of the
DAC’s thin film resistors. Simply placing a resistor in series
with the R
FB
resistor causes mismatches in the temperature
coefficients and results in larger gain temperature coefficient
errors. Instead, increase the gain of the circuit by using the
recommended configuration shown in Figure 48. R1, R2, and
R3 should have similar temperature coefficients, but they need
not match the temperature coefficients of the DAC. This
approach is recommended in circuits where gains greater than 1
are required.
04587-013
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
R
FB
I
OUT
1
GND
R1
V
REF
V
IN
V
DD
V
DD
C1
V
OUT
R3
R2
GAIN =
R2 + R3
R2
R1 =
R2R3
R2 + R3
Figure 48. Increasing Gain of Current-Output DAC