Datasheet

Data Sheet AD5444/AD5446
Rev. E | Page 5 of 28
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. V
DD
= 2.5 V to 5.5 V,
V
REF
= 10 V, I
OUT
2 = 0 V, temperature range for Y version: −40°C to +125°C; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1
V
DD
= 4.5 V to
5.5 V
V
DD
= 2.5 V to
5.5 V Unit Conditions/Comments
f
SCLK
50 50 MHz max Maximum clock frequency.
t
1
20 20 ns min SCLK cycle time.
t
2
8 8 ns min SCLK high time.
t
3
8 8 ns min SCLK low time.
t
4
8 8 ns min
SYNC
falling edge to SCLK active edge setup time.
t
5
5 5 ns min Data setup time.
t
6
4.5 4.5 ns min Data hold time.
t
7
5 5 ns min
SYNC
rising edge to SCLK active edge setup time
t
8
30 30 ns min
Minimum SYNC
high time.
t
9
23 30 ns min SCLK active edge to SDO valid.
Update Rate 2.7 2.7 MSPS
Consists of cycle time, SYNC
high time, data setup time and output
voltage settling time.
1
Guaranteed by design and characterization; not subject to production test.
0
4588-002
t
7
t
1
t
3
t
2
t
4
t
5
t
6
DB15 DB0
SCLK
SYNC
SDIN
t
8
Figure 2. Standalone Timing Diagram
DB15 (N) DB0 (N)
DB15
(N + 1)
DB0
(N + 1)
SCLK
SDIN
SDO
NOTES
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA IS CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.
t
4
t
5
t
6
t
2
t
1
t
3
t
7
t
8
t
9
DB15 (N)
DB0 (N)
S
YNC
04588-003
Figure 3. Daisy-Chain Timing Diagram