Datasheet

AD5444/AD5446 Data Sheet
Rev. E | Page 4 of 28
Parameter Min Typ Max Unit Conditions
DYNAMIC PERFORMANCE
1
Reference Multiplying Bandwidth 12 MHz V
REF
= ±3.5 V, DAC loaded with all 1s
Multiplying Feedthrough Error V
REF
= ±3.5 V, DAC loaded with all 0s
72 dB 100 kHz
64
dB
1 MHz
44 dB 10 MHz
Output Voltage Settling Time V
REF
= 10 V, R
LOAD
= 100 Ω, DAC latch alternately
loaded with 0s and 1s
Measured to ±1 mV of FS 100 110 ns
Measured to ±4 mV of FS 24 40 ns
Measured to ±16 mV of FS
16
33
ns
Digital Delay 20 40 ns Interface delay time
10%-to-90% Settling Time 10 30 ns Rise and fall time, V
REF
= 10 V, R
LOAD
= 100 Ω
Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, V
REF
= 0 V
Output Capacitance
I
OUT
1 13 pF DAC latches loaded with all 0s
28 pF DAC latches loaded with all 1s
I
OUT
2 18 pF DAC latches loaded with all 0s
5 pF DAC latches loaded with all 1s
Digital Feedthrough 0.5 nV-s Feedthrough to DAC output with
CS
high and
alternate loading of all 0s and all 1s
Analog THD 83 dB V
REF
= 3.5 V p-p, all 1s loaded, f = 1 kHz
Digital THD Clock = 1 MHz, V
REF
= 3.5 V
50 kHz f
OUT
71 dB
20 kHz f
OUT
77 dB
Output Noise Spectral Density 25 nV/√Hz @ 1 kHz
SFDR Performance (Wide Band) Clock = 10 MHz, V
REF
= 3.5 V
50 kHz f
OUT
78 dB
20 kHz f
OUT
74 dB
SFDR Performance (Narrow Band) Clock = 1 MHz, V
REF
= 3.5 V
50 kHz f
OUT
87 dB
20 kHz f
OUT
85 dB
Intermodulation Distortion
79
dB
f
1
= 20 kHz, f
2
= 25 kHz, clock = 1 MHz, V
REF
= 3.5 V
POWER REQUIREMENTS
Power Supply Range, V
DD
2.5
5.5
V
Supply Current, I
DD
0.4 10 µA T
A
= −40°C to +125°C, logic inputs = 0 V or V
DD
0.6 µA T
A
= 25°C, logic inputs = 0 V or V
DD
Power Supply Sensitivity
1
0.001 %/% ∆V
DD
= ±5%
1
Guaranteed by design and characterization; not subject to production test.