Datasheet

Data Sheet AD5426/AD5432/AD5443
Rev. G | Page 5 of 24
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. V
DD
= 2.5 V to 5.5 V,
V
REF
= 10 V, I
OUT
2 = 0 V; temperature range for Y version: −40°C to +125°C; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter 2.5 V to 5.5 V 4.5 V to 5.5 V Unit Test Conditions/Comments
f
SCLK
50 50 MHz max Max clock frequency
t
1
20 20 ns min SCLK cycle time
t
2
8 8 ns min SCLK high time
t
3
8 8 ns min SCLK low time
t
4
1
13 13 ns min
SYNC
falling edge to SCLK active edge setup time
t
5
5 5 ns min Data setup time
t
6
3 3 ns min Data hold time
t
7
5 5 ns min
SYNC
rising edge to SCLK active edge
t
8
30 30 ns min
Minimum SYNC
high time
t
9
2, 3
80 45 ns typ SCLK active edge to SDO valid
120 65 ns max
1
Falling or rising edge as determined by control bits of serial word.
2
Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with load circuit, as shown in Figure 4.
3
SDO operates with a VDD of 3.0 V to 5.5 V.
DB15 DB0
SCLK
SYNC
DIN
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF
SCLK AS DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED.
t
1
t
8
t
4
t
3
t
2
t
5
t
6
t
7
03162-002
Figure 2. Standalone Mode Timing Diagram
DB15 (N) DB0 (N)
 DB15
(N + 1)
DB0
(N + 1)
SCLK
SDIN
SDO
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED.
t6
DB15(N)
DB0(N)
t
1
t
2
t
5
t
9
t
6
t
4
t
3
t
7
t
8
SYNC
03162-003
Figure 3. Daisy-Chain and Readback Modes Timing Diagram