Datasheet

AD5441
Rev. A | Page 4 of 16
TIMING CHARACTERISTICS
All input control signals are specified with t
R
= t
F
= 2 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2; V
DD
+ 2.5 V
to 5.5 V, V
REF
= 10 V; temperature range = −40°C to +125°C; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2. Timing Characteristics
Parameter 2.5 V 5.5 V Unit Conditions/Comments
t
DS
10 5 ns min Data setup
t
DH
5 5 ns min Data hold
t
CH
15 10 ns min Clock width high
t
CL
15 10 ns min Clock width low
t
LD
20 10 ns min Load pulse width
t
LD1
0 0 ns min
LD
DAC high to MSB CLK high
t
ASB
0 0 ns min
LSB CLK to LD
DAC
Timing Diagrams
SRI
CLK
LD
D11
D10D9D8 D6D5D4D3D2D1D0D7
t
LD1
t
ASB
DAC REGISTER LOAD
0
6492-102
Figure 2. Full Data Transmission
SRI
CLK
t
DS
t
DH
t
CL
t
CH
Dxx
DATA LOADED MSB(D11) FIRST
0
6492-103
Figure 3. Bit Data Transmission
FS
ZS
V
OUT
t
LD
±1LSB
ERROR BAND
LD
06492-104
Figure 4. Output Transition
Table 3. Control Logic Truth Table
CLK
LD
Serial Shift Register Function DAC Register Function
↑
1
H Shift register data advanced one bit Latched
↑
L Shift register data advanced one bit Transparent
H or L L No effect Updated with current shift register contents
L
↑
1
No effect Latched all 12 bits
1
equals positive logic transition. ↑