Datasheet

AD5441
Rev. A | Page 12 of 16
BIPOLAR 4-QUADRANT MULTIPLYING
Figure 24 shows a suggested circuit to achieve 4-quadrant
multiplying operation. The summing amplifier multiplies V
OUT1
by 2 and offsets the output with the reference voltage so that a
midscale digital input code of 2048 places V
OUT2
at 0 V. The negative
full-scale voltage is V
REF
when the DAC is loaded with all zeros.
The positive full-scale output is −(V
REF
− 1 LSB) when the DAC
is loaded with all ones. Therefore, the digital coding is offset
binary. The voltage output transfer equation for various input
data and reference (or signal) values follows
V
OUT2
= (D/2048 − 1) − V
REF
where:
D is the decimal data loaded into the DAC register.
V
REF
is the externally applied reference voltage source.
INTERFACE LOGIC INFORMATION
The AD5441 has been designed for ease of operation. The
timing diagram in Figure 2 illustrates the input register loading
sequence. Note that the most significant bit (MSB) is loaded
first. Once the 12-bit input register is full, the data is transferred
to the DAC register by taking
LD
momentarily low.
DIGITAL SECTION
The digital inputs of the AD5441, SRI,
LD
, and CLK, are TTL-
compatible. The input voltage levels affect the amount of current
drawn from the supply; peak supply current occurs as the digital
input (V
IN
) passes through the transition region. See
for the supply current vs. logic input voltage graph. Maintaining
the digital input voltage levels as close as possible to the supplies,
V
DD
and GND, minimizes supply current consumption. The
digital inputs of the AD5441 were designed with ESD resistance
incorporated through careful layout and the inclusion of input
protection circuitry. shows the input protection diodes
and series resistor; this input structure is duplicated on each
digital input. High voltage static charges applied to the inputs
are shunted to the supply and ground rails through forward-
biased diodes. These protection diodes were designed to clamp
the inputs to well below dangerous levels during static discharge
conditions.
Figure 15
Figure 23
V
DD
LD, CLK, SRI
GND
5kΩ
06492-020
Figure 23. Digital Input Protection
06492-024
NOTES
1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR V
OUT
= 0V WITH CODE 10000000 LOADED TO DAC.
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R3 AND R4.
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
R
FB
I
OUT
1
GND
V
REF
±10V
V
REF
R1
AD5441
V
DD
V
DD
AGND
C1
A1
A2
R2
V
OUT
= –V
REF
TO +V
REF
µCONTROLLER
R3
20kΩ
R4
10kΩ
R5
20kΩ
CLK SRILD
Figure 24. Bipolar (4-Quadrant) Operation