Datasheet

Data Sheet AD5429/AD5439/AD5449
Rev. E | Page 5 of 28
TIMING CHARACTERISTICS
All input signals are specified with t
R
= t
F
= 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. V
DD
= 2.5 V to 5.5 V,
V
REF
= 10 V, I
OUT
2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1
Limit at T
MIN
, T
MAX
Unit Conditions/Comments
2
f
SCLK
50 MHz max Maximum clock frequency
t
1
20 ns min SCLK cycle time
t
2
8 ns min SCLK high time
t
3
8 ns min SCLK low time
t
4
13 ns min
SYNC
falling edge to SCLK falling edge setup time
t
5
5 ns min Data setup time
t
6
4 ns min Data hold time
t
7
5 ns min
SYNC
rising edge to SCLK falling edge
t
8
30 ns min Minimum
SYNC
high time
t
9
0 ns min SCLK falling edge to
LDAC
falling edge
t
10
12 ns min
LDAC
pulse width
t
11
10 ns min SCLK falling edge to
LDAC
rising edge
t
12
3
25 ns min SCLK active edge to SDO valid, strong SDO driver
60 ns min SCLK active edge to SDO valid, weak SDO driver
t
13
12 ns min
CLR
pulse width
t
14
4.5 ns min
SYNC
rising edge to
LDAC
falling edge
Update Rate 2.47 MSPS Consists of cycle time,
SYNC
high time, data setup, and output voltage settling time
1
Guaranteed by design and characterization, not subject to production test.
2
Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.
3
Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 5.
TIMING DIAGRAMS
t
1
t
2
t
3
t
7
t
8
t
4
t
5
t
6
t
9
t
10
t
11
DB15
DB0
SCLK
SDIN
LDAC
1
LDAC
2
SYNC
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPD
ATE MODE.
NOTES
1. ALTERNATIVELY, DATA CAN BE CLOCKED INTO THE INPUT SHIFT REGISTER ON THE RISING EDGE OF SCLK AS
DETERMINED BY THE CONTROL BITS. TIMING IS AS ABOVE, WITH SCLK INVERTED.
04464-002
Figure 2. Standalone Mode Timing Diagram