Datasheet

AD5429/AD5439/AD5449 Data Sheet
Rev. E | Page 4 of 28
Parameter
1
Min Typ Max Unit Conditions
Multiplying Feedthrough Error DAC latches loaded with all 0s, V
REF
= ±3.5 V
70 dB 1 MHz
48 dB 10 MHz
Output Capacitance 12 17 pF DAC latches loaded with all 0s
25
30
pF
DAC latches loaded with all 1s
Digital Feedthrough 3 5 nV-sec Feedthrough to DAC output with
CS
high and
alternate loading of all 0s and all 1s
Output Noise Spectral Density 25 nV/√Hz @ 1 kHz
Analog THD 81 dB V
REF
= 3. 5 V p-p, all 1s loaded, f = 1 kHz
Digital THD Clock = 10 MHz, V
REF
= 3.5 V
100 kHz f
OUT
61 dB
50 kHz f
OUT
66 dB
SFDR Performance (Wide Band) AD5449, 65k codes, V
REF
= 3.5 V
Clock = 10 MHz
500 kHz f
OUT
55 dB
100 kHz f
OUT
63 dB
50 kHz f
OUT
65 dB
Clock = 25 MHz
500 kHz f
OUT
50 dB
100 kHz f
OUT
60 dB
50 kHz f
OUT
62 dB
SFDR Performance (Narrow Band)
AD5449, 65k codes, V
REF
= 3.5 V
Clock = 10 MHz
500 kHz f
OUT
73 dB
100 kHz f
OUT
80 dB
50 kHz f
OUT
87 dB
Clock = 25 MHz
500 kHz f
OUT
70 dB
100 kHz f
OUT
75 dB
50 kHz f
OUT
80 dB
Intermodulation Distortion AD5449, 65k codes, V
REF
= 3.5 V
f
1
= 40 kHz, f
2
= 50 kHz 72 dB Clock = 10 MHz
f
1
= 40 kHz, f
2
= 50 kHz 65 dB Clock = 25 MHz
POWER REQUIREMENTS
Power Supply Range 2.5 5.5 V
I
DD
0.7
µA
T
A
= 25°C, logic inputs = 0 V or V
DD
0.5 10 µA T
A
= −40°C to +125°C, logic inputs = 0 V or V
DD
Power Supply Sensitivity 0.001 %/% ∆V
DD
= ±5%
1
Guaranteed by design and characterization, not subject to production test.