Datasheet

Data Sheet AD5425
Rev. C | Page 5 of 24
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. V
DD
=2.5 V to 5.5 V,
V
REF
= 10 V, I
OUT
2 = 0 V, temperature range for Y version: −40°C to +125°C ; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1
V
DD
= 2.5 V to 5.5 V Unit Conditions/Comments
f
SCLK
50 MHz max Maximum clock frequency
t
1
20 ns min SCLK cycle time
t
2
8 ns min SCLK high time
t
3
8 ns min SCLK low time
t
4
2
13 ns min
SYNC
falling edge to SCLK falling edge setup time
t
5
5 ns min Data setup time
t
6
3 ns min Data hold time
t
7
5 ns min
SYNC
rising edge to SCLK falling edge
t
8
30 ns min
Minimum
SYNC
high time
t
9
0 ns min
SCLK falling edge to
LDAC
falling edge
t
10
12 ns min
LDAC
pulse width
t
11
10 ns min
SCLK falling edge to
LDAC
rising edge
1
Guaranteed by design and characterization, not subject to production test.
2
Falling or rising edge as determined by control bits of serial word.
Figure 2. Timing Diagram
t
8
SCLK
SYNC
DIN
LDAC
2
LDAC
1
DB7
t
4
DB0
NOTES:
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
t
11
t
10
t
1
t
9
t
5
t
6
t
2
t
3
t
7
03161-002