Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 24 EP

Single Channel, 12-/16-Bit, Serial Input, Current

Source and Voltage Output DACs, HART Connectivity

Data Sheet

AD5412/AD5422

Rev. O Document Feedback

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FEATURES

12-/16-bit resolution and monotonicity

Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or

0 mA to 24 mA

±0.01% FSR typical total unadjusted error (TUE)

±3 ppm FSR/°C output drift

Voltage output ranges: 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V

10% overrange

±0.01% FSR typical TUE

±2 ppm FSR/°C output drift

Flexible serial digital interface

On-chip output fault detection

On-chip reference: 10 ppm/°C maximum

Optional regulated DV

output

Asynchronous clear function

Power supply range

: 10.8 V to 40 V

: −26.4 V to −3 V/0 V

Current loop compliance voltage: AV

– 2.5 V

Temperature range: −40°C to +105°C

TSSOP and LFCSP packages

APPLICATIONS

Process controls

Actuator controls

PLC

HART network connectivity (LFCSP package only)

GENERAL DESCRIPTION

The AD5412/AD5422 are low cost, precision, fully integrated

12-/16-bit digital-to-analog converters (DAC) offering a pro-

grammable current source and programmable voltage output

designed to meet the requirements of industrial process control

applications.

The output current range is programmable at 4 mA to 20 mA,

0 mA to 20 mA, or an overrange function of 0 mA to 24 mA.

The LFCSP version of this product has a CAP2 pin so that the

HART signals can be coupled onto the current output of the

AD5412/AD5422.

Voltage output is provided from a separate pin that can be

configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V

output ranges; an overrange of 10% is available on all ranges.

Analog outputs are short and open-circuit protected and can

drive capacitive loads of 1 µF.

The device operates with an AV

power supply range from 10.8 V

to 40 V. Current loop compliance voltage is 0 V to AV

− 2.5 V.

The flexible serial interface is SPI- and MICROWIRE™-compatible

and can be operated in 3-wire mode to minimize the digital

isolation required in isolated applications.

The device also includes a power-on-reset function, ensuring

that the device powers up in a known state. The part also includes

an asynchronous clear pin (CLEAR) that sets the outputs to

zero-scale/midscale voltage output or the low end of the

selected current range.

The total output error is typically ±0.01% in current mode and

±0.01% in voltage mode.

Table 1. Pin-Compatible Devices

Part No. Description

AD5410 Single channel, 12-bit, serial input current source DAC

AD5420 Single channel, 16-bit, serial input current source DAC

COMPANION PRODUCTS

HART Modem: AD5700, AD5700-1

Downloaded from Arrow.com.

Summary of content (44 pages)

PAGE 1
Single Channel, 12-/16-Bit, Serial Input, Current Source and Voltage Output DACs, HART Connectivity AD5412/AD5422 Data Sheet FEATURES GENERAL DESCRIPTION 12-/16-bit resolution and monotonicity Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or 0 mA to 24 mA ±0.01% FSR typical total unadjusted error (TUE) ±3 ppm FSR/°C output drift Voltage output ranges: 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V 10% overrange ±0.
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AD5412/AD5422 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Fault Alert .................................................................................... 35 Applications ....................................................................................... 1 Voltage Output Short Circuit Protection ................................ 35 General Description ..........................................................
PAGE 3
Data Sheet AD5412/AD5422 REVISION HISTORY 10/2017—Rev. N to Rev. O Changed CP-40-10 to CP-40-1 .................................... Throughout Updated Outline Dimensions ........................................................43 Changes to Ordering Guide ...........................................................44 3/2017—Rev. M to Rev. N Changed CP-40-9 to CP-40-10 .................................... Throughout Changes to Table 6 ..........................................................................
PAGE 4
AD5412/AD5422 Data Sheet FUNCTIONAL BLOCK DIAGRAM DVCC SELECT CLEAR SELECT DVCC AD5412/AD5422 *CAP1 *CAP2 AVSS AVDD R2 4.5V LDO R3 BOOST CLEAR LATCH SCLK SDIN SDO INPUT SHIFT REGISTER AND CONTROL LOGIC 12/16 12-/16-BIT DAC IOUT FAULT RSET POWER-ON RESET RSET VREF +VSENSE RANGE SCALING VOUT REFOUT GND REFIN *PINS ONLY ON LFCSP OPTION. Figure 1. Rev. O | Page 4 of 44 Downloaded from Arrow.com.
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Data Sheet AD5412/AD5422 SPECIFICATIONS AVDD = 10.8 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V. VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 6
AD5412/AD5422 Parameter 1 OUTPUT CHARACTERISTICS3 Headroom Output Voltage Drift vs. Time Short-Circuit Current Load Capacitive Load Stability RLOAD = ∞ RLOAD = 1 kΩ RLOAD = ∞ Data Sheet Min Accuracy (Internal RSET) Resolution TUE B Version A Version INL 4 DNL Offset Error Full-Scale TC3 Test Conditions/Comments 0.5 90 20 0.8 V ppm FSR mA kΩ Output unloaded Drift after 1000 hours, TA = 125°C 20 5 1 nF nF µF 130 12 Ω µs µV/V µV/V 24 20 20 mA mA mA 0.3 10 90 3 0 0 4 16 12 −0.3 −0.13 −0.5 −0.
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Data Sheet Parameter 1 Accuracy (External RSET) Resolution TUE B Version A Version INL4 DNL Offset Error AD5412/AD5422 Min Gain TC3 Full-Scale Error −0.15 −0.06 −0.3 −0.1 −0.012 −0.032 −1 −1 −0.1 −0.12 −0.03 −0.08 −0.15 −0.05 −0.15 −0.06 Full-Scale Error TC3 OUTPUT CHARACTERISTICS3 Current Loop Compliance Voltage Output Current Drift vs. Time Max 16 12 Offset Error TC3 Gain Error Typ ±0.01 ±0.02 ±0.006 ±3 ±5 ±0.003 ±4 ±0.01 ±7 ±9 0 +0.15 +0.06 +0.3 +0.1 +0.012 +0.032 +1 +1.3 +0.1 +0.12 +0.
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AD5412/AD5422 Parameter 1 DIGITAL INPUTS3 Input High Voltage, VIH Input Low Voltage, VIL Input Current Pin Capacitance DIGITAL OUTPUTS3 SDO Output Low Voltage, VOL Output High Voltage, VOH High Impedance Leakage Current High Impedance Output Capacitance FAULT Output Low Voltage, VOL Output Low Voltage, VOL Output High Voltage, VOH POWER REQUIREMENTS AVDD AVSS |AVSS| + AVDD DVCC Input Voltage Output Voltage Output Load Current3 Short-Circuit Current3 AIDD Data Sheet Min Typ Max Unit 0.
PAGE 9
Data Sheet AD5412/AD5422 AVDD = 15 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V. VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted. Voltage over range enabled. Table 3.
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AD5412/AD5422 Data Sheet AC PERFORMANCE CHARACTERISTICS AVDD = 10.8 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8 V, GND = 0 V, REFIN = +5 V external; DVCC = 2.7 V to 5.5 V. VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter 1 DYNAMIC PERFORMANCE Voltage Output Output Voltage Settling Time Min Typ Max Unit Test Conditions/Comments 25 8 0.8 10 10 20 1 0.
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Data Sheet Parameter 1, 2, 3 READBACK MODE t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 DAISY-CHAIN MODE t21 t22 t23 t24 t25 t26 t27 t28 t29 AD5412/AD5422 Limit at TMIN, TMAX Unit Description 90 40 40 13 40 5 5 40 35 35 ns min ns min ns min ns min ns min ns min ns min ns min ns max ns max SCLK cycle time SCLK low time SCLK high time LATCH delay time LATCH high time Data setup time Data hold time LATCH low time Serial output delay time (CL SDO 4 = 15 pF) LATCH rising edge to SDO tristate (CL SDO4 = 15 pF)
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AD5412/AD5422 Data Sheet t11 SCLK 1 1 24 2 t12 t13 t14 2 8 22 9 24 23 t15 LATCH t17 SDIN t18 DB23 DB0 DB23 DB0 NOP CONDITION INPUT WORD SPECIFIES REGISTER TO BE READ SDO X X X X DB15 DB0 SELECTED REGISTER DATA CLOCKED OUT FIRST 8 BITS ARE DON’T CARE BITS UNDEFINED DATA t20 t19 06996-003 t16 Figure 3.
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Data Sheet AD5412/AD5422 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Transient currents of up to 80 mA do not cause SCR latch-up. Table 6.
PAGE 14
AD5412/AD5422 Data Sheet NC DVCC NC AVSS AVDD NC –VSENSE +VSENSE VOUT NC PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 24 AVDD 23 –VSENSE FAULT 3 22 +VSENSE 21 VOUT 20 BOOST 19 IOUT 18 NC SCLK 8 17 CCOMP SDIN 9 16 DVCC SELECT SDO 10 15 REFIN GND 11 14 REFOUT GND 12 13 RSET 7 NC 1 FAULT 2 GND 3 CLEAR SELECT 4 CLEAR 5 LATCH 6 SCLK 7 SDIN 8 SDO 9 NC 10 AD5412/ AD5422 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 NC CAP2 CAP1 BOOST IOUT NC CCOMP DVCC SELECT NC NC NO
PAGE 15
Data Sheet TSSOP 16 AD5412/AD5422 Pin No. LFCSP 23 Mnemonic DVCC SELECT 17 24 CCOMP 19 20 26 27 IOUT BOOST N/A 28, 29 CAP1, CAP2 21 32 VOUT 22 23 24 25 (EPAD) 33 34 36 41 (EPAD) +VSENSE −VSENSE AVDD Exposed paddle Description When connected to GND, this pin disables the internal supply, and an external supply must be connected to the DVCC pin. Leave this pin unconnected to enable the internal supply. In this case, it is recommended to connect a 0.1 μF capacitor between DVCC and GND.
PAGE 16
AD5412/AD5422 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS GENERAL 900 9 TA = 25°C DVCC OUTPUT VOLTAGE (V) 700 DICC (µA) 600 DVCC = 5V 500 400 300 200 DVCC = 3V 0 0.5 1.0 1.5 7 6 5 4 3 2 1 2.0 2.5 3.0 3.5 LOGIC VOLTAGE (V) 4.0 4.5 5.0 06996-022 100 0 TA = 25°C 8 0 –21 Figure 7. DICC vs. Logic Input Voltage –19 –17 –15 –13 –11 –9 –7 –5 LOAD CURRENT (mA) –3 –1 1 Figure 10. DVCC Output Voltage vs.
PAGE 17
Data Sheet AD5412/AD5422 45 AVDD = 24V 40 POPULATION (%) 35 1 30 25 20 15 10 M2.00s LINE 0V 0 0 2 3 4 5 6 7 8 TEMPERATURE COEFFICIENT (ppm/°C) 9 10 Figure 15. Reference Temperature Coefficient Histogram Figure 13. REFOUT Output Noise (100 kHz Bandwidth) 5.003 5.0005 50 DEVICES SHOWN AVDD = 24V TA = 25°C AVDD = 24V 5.0000 REFERENCE OUTPUT VOLTAGE (V) REFERENCE OUTPUT VOLTAGE (V) 1 06996-030 CH1 20µV 06996-027 5 5.002 5.001 5.000 4.999 4.998 4.9995 4.9990 4.9985 4.9980 4.9975 4.
PAGE 18
AD5412/AD5422 Data Sheet VOLTAGE OUTPUT 0.0020 0.0015 0.6 0.0010 0.4 0.0005 0 –0.0005 –0.0010 ±10V RANGE ±5V RANGE +5V RANGE +10V RANGE –0.0015 –0.0020 20,000 30,000 40,000 CODE 50,000 60,000 Figure 17. Integral Nonlinearity Error vs. DAC Code, Dual Supply 0 0 –0.0005 –0.0010 –0.0015 –0.0020 10,000 20,000 30,000 40,000 50,000 60,000 CODE 60,000 0.001 –0.001 –0.003 –0.005 ±10V RANGE ±5V RANGE +5V RANGE +10V RANGE –0.007 0 10,000 20,000 30,000 40,000 CODE 50,000 60,000 Figure 21.
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Data Sheet AD5412/AD5422 0.012 0.0015 AVDD = +24V AVSS = –24V 0 –0.0005 –0.0015 –40 +5V RANGE MAX INL ±5V RANGE MAX INL +5V RANGE MIN INL ±5V RANGE MIN INL –20 0 +10V RANGE MAX INL ±10V RANGE MAX INL +10V RANGE MIN INL ±10V RANGE MIN INL 20 40 TEMPERATURE (°C) 60 80 0.008 0.006 0.004 0.002 0 –0.002 –0.006 –0.008 –40 Figure 23. Integral Nonlinearity Error vs. Temperature 1.0 0 20 40 TEMPERATURE (°C) 60 80 1.5 1.0 0.4 OFFSET ERROR (mV) DNL ERROR (LSB) 0.6 –20 Figure 26.
PAGE 20
AD5412/AD5422 0.014 Data Sheet 1.0 AVDD = +24V AVSS = –24V OUTPUT UNLOADED 0.012 0.6 0.008 0.4 DNL ERROR (LSB) 0.006 0.004 0.002 0 –0.002 –0.006 –0.008 –40 –20 0 –0.2 –0.4 –0.8 0 20 40 TEMPERATURE (°C) 60 80 –1.0 10 12 14 16 18 20 AVDD/|AVSS| (V) 26 28 0.0050 1.3 TOTAL UNADJUSTED ERROR (% FSR) AVDD = +24V AVSS = –24V OUTPUT UNLOADED 0.3 –0.2 –0.7 –1.2 –40 –20 0 20 40 TEMPERATURE (°C) 60 0.0040 0.0035 TA = 25°C ±10V RANGE 0.0030 0.0025 0.0020 0.0015 0.0010 0.
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Data Sheet AD5412/AD5422 0 12 8 OUTPUT VOLTAGE (V) –0.4 –0.6 –0.8 –1.0 –1.2 AVDD = +24V AVSS = –24V ±10V RANGE TA = 25°C OUTPUT UNLOADED 4 0 –4 –1.4 5 10 15 20 25 30 35 RLOAD (kΩ) –12 –10 –5 Figure 35.VOUT Footroom 0.02 0 –0.01 –0.02 –0.03 4 –10 –5 0 5 10 SOURCE/SINK CURRENT (mA) 15 20 0 –5 10 15 TIME (µs) 20 30 2 OUTPUT VOLTAGE (mV) 0 0 –0.02 –2 –6 –8 –10 –12 –0.04 –14 –15 –10 –5 0 5 10 SOURCE/SINK CURRENT (mA) 15 20 Figure 37.
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AD5412/AD5422 Data Sheet 35 AVDD = +15V AVSS = –15V TA = 25°C 30 VOUT (mV) 25 1 20 15 10 M 5.00ms LINE 0 1.8V Figure 41. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth) CH1 50.0µV M 5.00ms LINE 06996-038 0V Figure 42. Peak-to-Peak Noise (100 kHz Bandwidth) Rev. O | Page 22 of 44 Downloaded from Arrow.com. 2 4 6 8 10 12 TIME (µs) 14 16 Figure 43. VOUT vs. Time on Power-Up 1 AVDD = +24V AVSS = –24V TA = 25°C 0 18 20 06996-039 CH1 5.
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Data Sheet AD5412/AD5422 CURRENT OUTPUT 0.004 EXTERNAL RSET INTERNAL RSET EXTERNAL RSET, BOOST TRANSISTOR INTERNAL RSET , BOOST TRANSISTOR 0.002 INL ERROR (% FSR) 0 –0.002 –0.004 –0.006 AVDD = 24V AVSS = –24V/0V TA = 25°C RLOAD = 250Ω 0 10,000 20,000 30,000 40,000 CODE 50,000 60,000 0.6 0.003 0.002 INL ERROR (% FSR) 0.2 0 –0.2 –0.4 EXTERNAL RSET INTERNAL RSET EXTERNAL RSET, BOOST TRANSISTOR INTERNAL RSET, BOOST TRANSISTOR –0.8 –1.
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AD5412/AD5422 0.015 AVDD = 24V AVSS = –24V/0V 0.010 INL ERROR (% FSR) 0 –0.05 –0.10 4mA TO 20mA INTERNAL R SET 0mA TO 20mA INTERNAL R SET 0mA TO 24mA INTERNAL R SET 4mA TO 20mA EXTERNAL RSET 0mA TO 20mA EXTERNAL RSET 0mA TO 24mA EXTERNAL RSET –20 0 20 40 TEMPERATURE (°C) 60 80 –0.015 AVDD = 24V AVSS = –24V/0V 0.015 INL ERROR (% FSR) –0.05 –0.
PAGE 25
Data Sheet AD5412/AD5422 2.5 1.0 0.8 TA = 25°C 0mA TO 24mA RANGE AVSS = 0V 0.4 2.0 HEADROOM VOLTAGE (V) DNL ERROR (LSB) 0.6 AVDD = 15V AVSS = 0V IOUT = 24mA RLOAD = 500Ω 0.2 0 –0.2 –0.4 1.5 1.0 0.5 –0.6 10 15 25 20 30 35 40 AVDD (V) 0 –40 06996-015 Figure 56. Differential Nonlinearity Error vs. AVDD, Internal RSET 0.020 AVDD = 24V AVSS = 0V TA = 25°C RLOAD = 250Ω 3.0 OUTPUT CURRENT (µA) 0.015 0.010 0.005 0 –0.005 2.5 2.0 1.5 1.
PAGE 26
AD5412/AD5422 Data Sheet 70 25 60 OUTPUT CURRENT (mA) 40 30 20 TA = 25°C AVDD = 40V AVSS = 0V OUTPUT DISABLED 0 5 10 15 20 25 30 35 COMPLIANCE VOLTAGE (V) 40 45 Figure 62. Output Leakage Current vs. Compliance Voltage OUTPUT CURRENT (µA) 0x8000 TO 0x7FFF 0x7FFF TO 0x8000 AVDD = 24V AVSS = 0V TA = 25°C RLOAD = 250Ω 10 0 –10 06996-049 –20 –30 0 2 4 6 8 10 12 TIME (µs) 14 16 18 20 Figure 63. Digital to Analog Glitch Rev. O | Page 26 of 44 Downloaded from Arrow.com.
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Data Sheet AD5412/AD5422 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or INL, is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 17. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed in % FSR. A plot of gain error vs.
PAGE 28
AD5412/AD5422 Data Sheet Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. Voltage Reference TC Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature.
PAGE 29
Data Sheet AD5412/AD5422 THEORY OF OPERATION ARCHITECTURE The DAC core architecture of the AD5412/AD5422 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 65. The four MSBs of the 12-/16-bit data-word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of 15 matched resistors to either ground or the reference buffer output.
PAGE 30
AD5412/AD5422 Data Sheet SERIAL INTERFACE CONTROLLER The AD5412/AD5422 are controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 MHz. It is compatible with SPI, QSPI™, MICROWIRE, and DSP standards. DATA OUT Input Shift Register The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. Data is clocked in on the rising edge of SCLK.
PAGE 31
Data Sheet AD5412/AD5422 Readback Operation Voltage Output Readback mode is invoked by setting the address byte and read address when writing to the input register (see Table 10 and Table 12). The next write to the AD5412/AD5422 should be a NOP command, which clocks out the data from the previously addressed register as shown in Figure 3.
PAGE 32
AD5412/AD5422 Data Sheet POWER-ON SOFTWARE RESET CONTROL REGISTER WRITE (ONE WRITE COMMAND) • SELECT RSET EXTERNAL/INTERNAL • SET THE REQUIRED RANGE • CONFIGURE THE SLEW RATE CONTROL (IF REQUIRED) • CONFIGURE DAISY CHAIN MODE (IF REQUIRED) • ENABLE THE OUTPUT CONTROL REGISTER WRITE • DISABLE OUTPUT DATA REGISTER WRITE RSET CONFIGURATION CHANGE RANGE CHANGE Figure 69. Programming Sequence to Write/Enable the Output Correctly Rev. O | Page 32 of 44 Downloaded from Arrow.com.
PAGE 33
Data Sheet AD5412/AD5422 DATA REGISTER The data register is addressed by setting the address word of the input shift register to 0x01. The data to be written to the data register is entered in the D15 to D4 positions for the AD5412 and the D15 to D0 positions for the AD5422, as shown in Table 13 and Table 14. Table 13. Programming the AD5412 Data Register MSB D15 D14 D13 D12 D11 D10 D9 12-bit data-word D8 D7 D6 D5 D4 D3 X D2 X D1 X LSB D0 X D1 LSB D0 Table 14.
PAGE 34
AD5412/AD5422 Data Sheet RESET REGISTER The reset register is addressed by setting the address word of the input shift register to 0x56. The data to be written to the reset register is entered in the D0 position as shown in Table 18. The reset register options are shown in Table 18 and Table 19. Table 18. Programming the Reset Register MSB D15 D14 D13 D12 D11 D10 D9 D8 Reserved D7 D6 D5 D4 D3 D2 D1 LSB D0 Reset Table 19.
PAGE 35
Data Sheet AD5412/AD5422 AD5412/AD5422 FEATURES FAULT ALERT ASYNCHRONOUS CLEAR (CLEAR) The AD5412/AD5422 are equipped with a FAULT pin, which is an open-drain output allowing several AD5412/AD5422 devices to be connected together to one pull-up resistor for global fault detection.
PAGE 36
AD5412/AD5422 Data Sheet AVDD DIGITAL POWER SUPPLY EXTERNAL BOOST FUNCTION The addition of an external boost transistor, as shown in Figure 70, reduces the power dissipated in the AD5412/AD5422 by reducing the current flowing in the on-chip output transistor (dividing it by the current gain of the external circuit). A discrete NPN transistor with a breakdown voltage, BVCEO, greater than 40 V can be used.
PAGE 37
Data Sheet AD5412/AD5422 25 Update Clock Frequency (Hz) 257,730 198,410 152,440 131,580 115,740 69,440 37,590 25,770 20,160 16,030 10,290 8280 6900 5530 4240 3300 20 OUTPUT CURRENT (mA) 15 10 5 0 –10 10ms RAMP, SR CLOCK = 0x1, SR STEP = 0x5 50ms RAMP, SR CLOCK = 0xA, SR STEP = 0x7 100ms RAMP, SR CLOCK = 0x8, SR STEP = 0x5 0 10 20 30 40 50 60 TIME (ms) 80 90 100 110 IOUT FILTERING CAPACITORS (LFCSP PACKAGE) Capacitors can be placed between CAP1 and AVDD, and CAP2 and AVDD, as shown in Figure
PAGE 38
AD5412/AD5422 Data Sheet 6.8 C2 AVDD CAP2 4kΩ OUTPUT CURRENT (mA) CAP1 40Ω BOOST DAC TA = 25°C AVDD = 24V RLOAD = 300Ω 6.7 12.5kΩ IOUT 6.6 6.5 6.4 6.3 NO EXTERNAL CAPS 10nF ON CAP1 10nF ON CAP2 6.2 6.1 –1 06996-063 R1 0 1 2 3 4 TIME (ms) 5 6 7 06996-043 C1 8 Figure 76. Smoothing Out the Steps Caused by the Digital Slew Rate Control Feature Figure 74.
PAGE 39
Data Sheet AD5412/AD5422 APPLICATIONS INFORMATION AVDD VOLTAGE AND CURRENT OUTPUT RANGES ON THE SAME TERMINAL The current and voltage output pins can be connected together. A buffer amplifier is required, however, to prevent a current leakage path through an internal 30 kΩ resistor on the +VSENSE pin when the device is in current output mode. In current mode, the VOUT pin is high impedance; whereas in voltage output mode, the IOUT pin is high impedance and does not affect the voltage output.
PAGE 40
AD5412/AD5422 Data Sheet To ensure that the junction temperature does not exceed 125°C while driving the maximum current of 24 mA directly into ground (also adding an on-chip current of 3 mA), reduce AVDD from the maximum rating to ensure that the package is not required to dissipate more power than previously stated (see Table 26, Figure 80, and Figure 81). Avoid crossover of digital and analog signals. Traces on opposite sides of the PCB should run at right angles to each other.
PAGE 41
Data Sheet AD5412/AD5422 Table 26.
PAGE 42
AD5412/AD5422 Data Sheet 2.7V TO 5.5V 10µF 10µF 0.1µF 0.1µF 10kΩ C3 CAP1 DVCC DIGITAL INTERFACE UART INTERFACE 0V TO –26.4V REFIN CLEAR REFOUT LATCH SCLK SDIN SDO IOUT AD5412/ AD5422 +VSENSE AVSS 10µF 10.8V TO 26.4V AVDD FAULT RSET D4 0.1µF D2 RP OP1177 4mA TO 20mA CURRENTLOOP D3 D1 RL 500Ω RP 10kΩ AVSS VOUT –VSENSE 0.1µF TXD HART_OUT AVDD 1µF AD5700 1.2MΩ ADC_IP AGND DGND 300pF 150kΩ 150pF 1.2MΩ 06996-079 REF RTS CD C2 22nF C1 2.2nF VCC RXD GND CAP2 0.
PAGE 43
Data Sheet AD5412/AD5422 OUTLINE DIMENSIONS 5.02 5.00 4.95 7.90 7.80 7.70 24 13 4.50 4.40 4.30 1 3.25 3.20 3.15 EXPOSED PAD (Pins Up) 6.40 BSC 12 BOTTOM VIEW TOP VIEW 1.05 1.00 0.80 0.15 0.05 SEATING PLANE 0.10 COPLANARITY 0.65 BSC FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 8° 0° 0.20 0.09 0.30 0.19 0.75 0.60 0.45 061708-A 1.20 MAX COMPLIANT TO JEDEC STANDARDS MO-153-ADT Figure 84.
PAGE 44
AD5412/AD5422 Data Sheet ORDERING GUIDE Model 1 AD5412AREZ AD5412AREZ-REEL7 AD5412ACPZ-REEL AD5412ACPZ-REEL7 AD5422AREZ AD5422AREZ-REEL AD5422BREZ AD5422BREZ-REEL AD5422ACPZ-REEL AD5422ACPZ-REEL7 AD5422BCPZ-REEL AD5422BCPZ-REEL7 EVAL-AD5422EBZ EVAL-AD5422LFEBZ 1 Resolution (Bits) 12 12 12 12 16 16 16 16 16 16 16 16 IOUT TUE (% FSR max) 0.5 0.5 0.5 0.5 0.5 0.5 0.3 0.3 0.5 0.5 0.3 0.3 VOUT TUE (% FSR max) 0.3 0.3 0.3 0.3 0.3 0.3 0.1 0.1 0.3 0.3 0.1 0.