Datasheet

AD5412/AD5422 Data Sheet
Rev. I | Page 38 of 44
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration of
the power supply and ground return layout helps to ensure the
rated performance. Design the printed circuit board (PCB) on
which the AD5412/AD5422 is mounted so that the analog and
digital sections are separated and confined to certain areas of the
board. If the AD5412/AD5422 is in a system where multiple
devices require an analog ground-to-digital ground connection,
make the connection at one point only. Establish the star ground
point as close as possible to the device.
The AD5412/AD5422 should have ample supply bypassing of
10 µF in parallel with 0.1 µF on each supply located as close to
the package as possible, ideally right up against the device. The
10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low effective series resistance (ESR) and low effective
series inductance (ESI), such as the common ceramic types,
which provide a low impedance path to ground at high frequencies
to handle transient currents due to internal logic switching.
The power supply lines of the AD5412/AD5422 should use as
large a trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with a digital ground
to avoid radiating noise to other parts of the board. Never run these
near the reference inputs. A ground line routed between the SDIN
and SCLK lines helps reduce crosstalk between them (this is not
required on a multilayer board that has a separate ground plane,
but separating the lines helps). It is essential to minimize noise
on the REFIN line because it couples through to the DAC output.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the PCB should run at right angles to each
other. This reduces the effects of feed through the board. A
microstrip technique is by far the best but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane, and signal
traces are placed on the solder side.
THERMAL AND SUPPLY CONSIDERATIONS
The AD5412/AD5422 are designed to operate at a maximum
junction temperature of 125°C. It is important that the devices
not be operated under conditions that cause the junction
temperature to exceed this value. Excessive junction tempera-
ture can occur if the AD5412/AD5422 are operated from the
maximum AV
DD
while driving the maximum current (24 mA)
directly to ground. In this case, control the ambient temperature
or reduce AV
DD
. The conditions depend on the device package.
At the maximum ambient temperature of 85°C, the 24-lead TSSOP
package can dissipate 1.14 mW, and the 40-lead LFCSP package
can dissipate 1.21 W.
To ensure that the junction temperature does not exceed 125°C
while driving the maximum current of 24 mA directly into ground
(also adding an on-chip current of 3 mA), reduce AV
DD
from the
maximum rating to ensure that the package is not required to
dissipate more power than previously stated (see Table 25,
Figure 80, and Figure 81).
0
0.5
1.0
1.5
2.0
2.5
40
45 50
55 60 65 70 75
80
85
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
LFCSP
TSSOP
06996-066
Figure 80. Maximum Power Dissipation vs. Ambient Temperature
25
27
29
31
33
35
37
39
41
43
45
25 35 45 55 65 75 85
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
06996-067
TSSOP
LFCSP
Figure 81. Maximum Supply Voltage vs. Ambient Temperature