Datasheet

Data Sheet AD5412/AD5422
Rev. I | Page 35 of 44
Table 23. Slew Rate Update Clock Options
SR Clock Update Clock Frequency (Hz)
0000 257,730
0001 198,410
0010 152,440
0011 131,580
0100 115,740
0101 69,440
0110 37,590
0111 25,770
1000 20,160
1001
16,030
1010 10,290
1011 8280
1100 6900
1101 5530
1110 4240
1111
3300
The time it takes for the output to slew over a given output
range can be expressed as follows:
SizeLSBFrequencyClockUpdateSizeStep
ChangeOutput
TimeSlew
××
=
(1)
where:
Slew Time is expressed in seconds.
Output Change is expressed in amps for I
OUT
or volts for V
OUT
.
When the slew rate control feature is enabled, all output
changes change at the programmed slew rate; if the CLEAR
pin is asserted, the output slews to the zero-scale value at the
programmed slew rate. The output can be halted at its current
value with a write to the control register. To avoid halting the
output slew, the slew active bit (see Table 19) can be read to
check that the slew has completed before writing to any of the
AD5410/AD5420 registers. The update clock frequency for any
given value is the same for all output ranges. The step size,
however, varies across output ranges for a given value of step
size because the LSB size is different for each output range.
Table 24 shows the range of programmable slew times for a full-
scale change on any of the output ranges. The values in Table 24
were obtained using Equation 1.
The digital slew rate control feature results in a staircase
formation on the current output, as shown in Figure 76. This
figure also shows how the staircase can be removed by
connecting capacitors to the CAP1 and CAP2 pins, as described
in the I
OUT
Filtering Capacitors (LFCSP Package) section.
0
5
10
15
20
25
–10 0 10 20 30 40 50
60
70 80
90 100
110
OUTPUT CURRENT (mA)
TIME (ms)
T
A
= 25°C
AV
DD
= 24V
R
LOAD
= 300Ω
06996-139
10ms RAMP, SR CLOCK = 0x1, SR STEP = 0x5
50ms RAMP, SR CLOCK = 0xA, SR STEP = 0x7
100ms RAMP, SR CLOCK = 0x8, SR STEP = 0x5
Figure 72. Output Current Slewing Under Control of the Digital Slew Rate
Control Feature
I
OUT
FILTERING CAPACITORS (LFCSP PACKAGE)
Capacitors can be placed between CAP1 and AV
DD
, and CAP2
and AV
DD
, as shown in Figure 73.
CAP1
AV
DD
C1 C2
AV
DD
AD5412/
AD5422
CAP2
GND
06996-062
I
OUT
Figure 73. I
OUT
Filtering Capacitors
The CAP1 and CAP2 pins are available only on the LFCSP
package. The capacitors form a filter on the current output
circuitry, as shown in Figure 74, reducing the bandwidth and
the slew rate of the output current. Figure 75 shows the effect
the capacitors have on the slew rate of the output current. To
achieve significant reductions in the rate of change, very large
capacitor values are required, which may not be suitable in
some applications. In this case, the digital slew rate control
feature can be used. The capacitors can be used in conjunction
with the digital slew rate control feature as a means of
smoothing out the steps caused by the digital code increments,
as shown in Figure 76.