Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Companion Products
- Table of Contents
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Theory of Operation
- AD5412/AD5422 Features
- Fault Alert
- Voltage Output Short Circuit Protection
- Voltage Output Overrange
- Voltage Output Force-Sense
- Asynchronous Clear (CLEAR)
- Internal Reference
- External Current Setting Resistor
- Digital Power Supply
- External Boost Function
- External Compensation Capacitor
- HART Communication
- Digital Slew Rate Control
- IOUT Filtering Capacitors (LFCSP Package)
- Applications Information
- Outline Dimensions
Data Sheet AD5412/AD5422
Rev. I | Page 31 of 44
DATA REGISTER
The data register is addressed by setting the address word of the input shift register to 0x01. The data to be written to the data register is
entered in the D15 to D4 positions for the AD5412 and the D15 to D0 positions for the AD5422, as shown in Table 12 and Table 13.
Table 12. Programming the AD5412 Data Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
12-bit data-word X X X X
Table 13. Programming the AD5422 Data Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
16-bit data-word
CONTROL REGISTER
The control register is addressed by setting the address word of the input shift register to 0x55. The data to be written to the control
register is entered in the D15 to D0 positions, as shown in Table 14. The control register functions are shown in Table 15.
Table 14. Programming the Control Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CLRSEL OVRRNG REXT OUTEN SR clock SR step SREN DCEN R2 R1 R0
Table 15. Control Register Functions
Option
Description
CLRSEL See Table 21 for a description of the CLRSEL operation.
OVRRNG Setting this bit increases the voltage output range by 10% (see the AD5412/AD5422 Features section).
REXT
Setting this bit selects the external current setting resistor (see the AD5412/AD5422 Features section). When
using an external current setting resistor, it is recommended to only set REXT when also setting the OUTEN
bit. Alternately, REXT can be set before the OUTEN bit is set, but the range (see Table 16) must be changed
on the write in which the output is enabled. See Figure 69 for best practice.
OUTEN Output enable. This bit must be set to enable the outputs. The range bits select which output is functional.
SR clock
Digital slew rate control (see the AD5412/AD5422 Features section).
SR step Digital slew rate control (see the AD5412/AD5422 Features section).
SREN Digital slew rate control enable.
DCEN Daisy chain enable.
R2, R1, R0 Output range select (see Table 16).
Table 16. Output Range Options
R2 R1 R0 Output Range Selected
0
0
0
0 V to 5 V voltage range
0 0 1 0 V to 10 V voltage range
0 1 0 ±5 V voltage range
0 1 1 ±10 V voltage range
1 0 1 4 mA to 20 mA current range
1 1 0 0 mA to 20 mA current range
1 1 1 0 mA to 24 mA current range