Datasheet
Table Of Contents
- Features
- Applications
- General Description
- Companion Products
- Table of Contents
- Functional Block Diagram
- Specifications
- Absolute Maximum Ratings
- Pin Configurations and Function Descriptions
- Typical Performance Characteristics
- Terminology
- Theory of Operation
- AD5412/AD5422 Features
- Fault Alert
- Voltage Output Short Circuit Protection
- Voltage Output Overrange
- Voltage Output Force-Sense
- Asynchronous Clear (CLEAR)
- Internal Reference
- External Current Setting Resistor
- Digital Power Supply
- External Boost Function
- External Compensation Capacitor
- HART Communication
- Digital Slew Rate Control
- IOUT Filtering Capacitors (LFCSP Package)
- Applications Information
- Outline Dimensions

AD5412/AD5422 Data Sheet
Rev. I | Page 10 of 44
DB23
SCLK
LATCH
SDIN
24
2
1
DB0
t
2
t
3
t
1
t
4
t
8
t
7
t
6
t
9
t
10
t
5
CLEAR
I
OUT
/V
OUT
06996-002
Figure 2. Write Mode Timing Diagram
DB23
SCLK
LATCH
SDIN
2
4
2
1
DB0
SDO
DB23
SEL
E
C
T
E
D
R
EGIST
ER
DATA
CL
O
CKE
D O
U
T
NOP
C
OND
IT
IO
N
UNDEFINED DATA
INPUT WORD SPECIFIES
REGISTER TO BE READ
1
2
2
4
DB0
DB
15
DB0
X
XX
X
8
9
2
3
2
2
FIRST 8 BITS ARE
DON’T CARE BITS
t
2
0
t
19
t
17
t
12
t
13
t
14
t
11
t
15
t
16
t
18
06996-003
Figure 3. Readback Mode Timing Diagram
DB23 DB23
SCLK
SDIN
24
21
DB0 DB0
DB0
SDO
DB23
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N – 1
UNDEFINED
INPUT WORD FOR DAC N
25
4826
LATCH
DB23 DB0
t
20
t
28
t
27
t
26
t
29
t
22
t
23
t
21
t
24
t
25
06996-004
Figure 4. Daisy-Chain Mode Timing Diagram