Datasheet

Data Sheet AD5421
Rev. G | Page 11 of 36
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted. Transient currents of up
to 100 mA do not cause SCR latch-up.
Table 6.
Parameter Rating
REG
IN
to COM
−0.3 V to +60 V
REG
OUT
to COM −0.3 V to +14 V
Digital Inputs to COM,
RANGE0, RANGE1, R
INT
/R
EXT
,
ALARM_CURRENT_DIRECTION,
REG_SEL0, REG_SEL1, REG_SEL2
−0.3 V to DV
DD
+ 0.3 V
or +7 V (whichever is less)
Digital Inputs to COM
SCLK, SDIN,
SYNC, LDAC
−0.3 V to IODV
DD
+ 0.3 V
or +7 V (whichever is less)
Digital Outputs to COM,
SDO, FAULT
−0.3 V to IODV
DD
+ 0.3 V
or +7 V (whichever is less)
REFIN to COM −0.3 V to +7 V
REFOUT1, REFOUT2
−0.3 V to +4.7 V
V
LOOP
to COM −0.3 V to +60 V
LOOP− to COM −5 V to +0.3 V
DV
DD
to COM −0.3 V to +7 V
IODV
DD
to COM −0.3 V to +7 V
R
EXT1
, C
IN
to COM −0.3 V to +4.3 V
R
EXT2
to COM
−0.3 V to +0.3 V
DRIVE to COM −0.3 V to +11 V
Operating Temperature Range (T
A
)
Industrial −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (T
J MAX
) 125°C
Power Dissipation (T
J MAX
− T
A
)/θ
JA
Lead Temperature,
Soldering (10 sec)
JEDEC Industry Standard
J-STD-020
ESD
Human Body Model 3 kV
Field Induced Charged Device
Model
2 kV
Machine Model 200 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type θ
JA
1
θ
JC
Unit
28-Lead TSSOP_EP (RE-28-2) 32 9 °C/W
32-Lead LFCSP_WQ (CP-32-11) 40 7 °C/W
1
Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with thermal vias. See JEDEC JESD51.
ESD CAUTION