Datasheet

Data Sheet AD5421
Rev. G | Page 9 of 36
AC PERFORMANCE CHARACTERISTICS
Loop voltage = 24 V; REFIN = 2.5 V external; R
L
= 250 Ω; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
1
Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Loop Current Settling Time 50 µs To 0.1% FSR, C
IN
= open circuit
Loop Current Slew Rate 400 µA/µs C
IN
= open circuit
AC Loop Voltage Sensitivity 1.3 µA/V 1200 Hz to 2200 Hz, 5 V p-p, R
L
= 3 kΩ
1
Temperature range: −40°C to +105°C; typical at +25°C.
TIMING CHARACTERISTICS
Loop voltage = 24 V; REFIN = 2.5 V external; R
L
= 250 Ω; all specifications T
MIN
to T
MAX
.
Table 4.
Parameter
1, 2, 3
Limit at T
MIN
, T
MAX
Unit Description
t
1
33 ns min SCLK cycle time
t
2
17 ns min SCLK high time
t
3
17
ns min
SCLK low time
t
4
17 ns min
SYNC falling edge to SCLK falling edge setup time
t
5
10 ns min
SCLK falling edge to
SYNC rising edge
t
6
25 µs min
Minimum
SYNC high time
t
7
5 ns min Data setup time
t
8
5 ns min Data hold time
t
9
25 µs min
SYNC rising edge to LDAC falling edge
t
10
10 ns min
LDAC pulse width low
t
11
70 ns max SCLK rising edge to SDO valid (C
L SDO
= 30 pF)
t
12
0 ns min
SYNC falling edge to SCLK rising edge setup time
t
13
70 ns max
SYNC rising edge to SDO tristate (C
L SDO
= 30 pF)
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.2 V.
3
See Figure 2 and Figure 3.
Table 5. SPI Watchdog Timeout Periods
Parameter
1
Min Typ Max Unit
T0 T1 T2
0 0 0 43 50 59 ms
0 0 1 87 100 117 ms
0 1 0 436 500 582 ms
0 1 1 873 1000 1163 ms
1 0 0 1746 2000 2326 ms
1
0
1
2619
3000
3489
ms
1 1 0 3493 4000 4652 ms
1 1 1 4366 5000 5814 ms
1
Specifications guaranteed by design and characterization; not production tested.