Datasheet

AD5421 Data Sheet
Rev. G | Page 6 of 36
Parameter
1
Min Typ Max Unit Test Conditions/Comments
REG
OUT
OUTPUT Voltage regulator output
Output Voltage 1.8 12 V See Table 10
Output Voltage TC
3
110 ppm/°C
Output Voltage Accuracy −4 ±2 +4 %
Externally Available Current
3, 6
3.15
mA
Assuming 4 mA flowing in the loop
and during HART communications
Short-Circuit Current 23 mA
Line Regulation
3
500 μV/V Internal NMOS
10 μV/V External NMOS
Load Regulation
3
8 mV/mA
Inductive Load
50
mH
Stable operation
Capacitive Load 2 10 µF Recommended operation
ADC ACCURACY
Die Temperature ±5 °C
V
LOOP
Input ±1 %
DV
DD
OUTPUT Can be overdriven up to 5.5 V
Output Voltage 3.17 3.3 3.48 V
Externally Available Current
3, 6
3.15 mA
Assuming 4 mA flowing in the loop
and during HART communications
Short-Circuit Current 7.7 mA
Load Regulation 45 mV/mA Measured at 0 mA and 3 mA loads
DIGITAL INPUTS
3
SCLK,
SYNC, SDIN, LDAC
Input High Voltage, V
IH
0.7 × IODV
DD
V
Input Low Voltage, V
IL
0.25 × IODV
DD
V
Hysteresis
0.21
V
IODV
DD
= 1.8 V
0.63 V IODV
DD
= 3.3 V
1.46 V IODV
DD
= 5.5 V
Input Current −0.015 +0.015 µA Per pin
Pin Capacitance 5 pF Per pin
DIGITAL OUTPUTS
3
SDO Pin
Output Low Voltage, V
OL
0.4 V
Output High Voltage, V
OH
IODV
DD
− 0.5
V
High Impedance Leakage
Current
−0.01 +0.01 µA
High Impedance Output
Capacitance
5 pF
FAULT Pin
Output Low Voltage, V
OL
0.4
V
Output High Voltage, V
OH
IODV
DD
− 0.5 V
FAULT THRESHOLDS
I
LOOP
Under
I
LOOP
− 0.01% FSR
mA
I
LOOP
Over
I
LOOP
+ 0.01% FSR mA
Temp 140°C 133 °C
Fault removed when temperature
≤ 125°C
Temp 100°C 90 °C
Fault removed when temperature
≤ 85°C
V
LOOP
6V 0.3 V Fault removed when V
LOOP
≥ 0.4 V
V
LOOP
12V 0.6 V Fault removed when V
LOOP
≥ 0.7 V