Datasheet

AD5421 Data Sheet
Rev. G | Page 32 of 36
APPLICATIONS INFORMATION
Figure 50 shows a typical connection diagram for the AD5421
configured in a HART capable smart transmitter. Such a HART
enabled smart transmitter was developed by Analog Devices as
a reference demo circuit. This circuit, whose block diagram is
shown in Figure 51, was verified and registered as an approved
HART solution by the HART Communication Foundation.
This circuit is available as a Circuit from the Lab at CN0267,
Complete 4 mA to 20 mA Loop Powered Field Instrument with
HART Interface.
To reduce power dissipation on the chip, a depletion mode
MOSFET (T1), such as a DN2540 or BSP129, can be connected
between the loop voltage and the AD5421, as shown in Figure 50.
If a low loop voltage is used, T1 does not need to be inserted,
and the loop voltage can connect directly to REG
IN
(see Figure 43).
In Figure 50, all interface signal lines are connected to the micro-
controller. To reduce the number of interface signal lines, the
LDAC
signal can be connected to COM, and the SDO and FAULT
lines can be left unconnected. However, this configuration disables
the use of the fault alert features.
Under normal operating conditions, the voltage between COM
and LOOP− does not exceed 1.5 V, and the voltage at LOOP− is
negative with respect to COM. If it is possible that the voltage at
LOOP− may be forced positive with respect to COM, or if the
voltage difference between LOOP− and COM may be forced in
excess of 5 V, a 4.7 V low leakage Zener diode should be placed
between COM and the LOOP− pin, as shown in Figure 50, to
protect the AD5421 from potential damage.
DETERMINING THE EXPECTED TOTAL ERROR
The AD5421 can be set up in a number of different configu-
rations, each of which achieves different levels of accuracy, as
described in Table 1 and Table 2. With the internal voltage
reference and internal R
SET
enabled, a maximum total error
of 0.157% of full-scale range can be expected for the C grade
device over the temperature range of −40°C to +105°C.
Other configurations specify an external voltage reference, an
external R
SET
resistor, or both an external voltage reference and
external R
SET
resistor. In these configurations, the specifications
assume that the external voltage reference and external R
SET
resistor are ideal. Therefore, the errors associated with these
components must be added to the data sheet specifications to
determine the overall performance. The performance depends
on the specifications of these components.
09128-055
HART_OUT
ADC_IP
REF
AD5700/AD5700-1
47nF 168nF
300pF
V
CC
R
L
200kΩ
LOOP–
R
EXT1
R
EXT2
DRIVE
COMREFOUT1 REFIN REG_SEL0 REG_SEL1 REG_SEL2
REG
IN
IODV
DD
DV
DD
REG
OUT
V
LOOP
AD5421
19MΩ
1MΩ
V
LOOP
ADuCM360
SYNC
SCLK
SDIN
SDO
R
INT
/R
EXT
ALARM_CURRENT_DIRECTION
RANGE1
RANGE0
FAULT
LDAC
COM
TXD
RXD
RTS
CD
R1
R1
470Ω
1.2MΩ
150kΩ
1.2MΩ 150pF
OPTIONAL
RESISTOR
T1
OPTIONAL
MOSFET
DN2540
BSP129
0.1µF
SETS REGULATOR
VOLTAGE
C
IN
10µF
0.1µF
1µF
0.1µF
V
Z
= 4.7V
4.7µF
REFOUT2
OPTIONAL
EMC FILTER
1µF
DGNDAGND
Figure 50. AD5421 Application Diagram for HART Capable Smart Transmitter