Datasheet

AD5421 Data Sheet
Rev. G | Page 26 of 36
SERIAL INTERFACE
The AD5421 is controlled by a versatile, 3-wire serial interface
that operates at clock rates up to 30 MHz. It is compatible with
the SPI, QSPI™, MICROWIRE®, and DSP standards. Figure 2
shows the timing diagram. The interface operates with either
a continuous or noncontinuous gated burst clock.
The write sequence begins with a falling edge of the
SYNC
signal; data is clocked in on the SDIN data line on the falling
edge of SCLK. On the rising edge of
SYNC
, the 24 bits of data
are latched; the data is transferred to the addressed register and
the programmed function is executed (either a change in DAC
output or mode of operation).
If packet error checking on the SPI interface is required using
cyclic redundancy codes, an additional eight bits must be written
to the AD5421, creating a 32-bit serial interface. In this case,
32 bits are written to the AD5421 before
SYNC
is brought high.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (32 bits wide if CRC error
checking of the data is required). Data is loaded into the device
MSB first as a 24-/32-bit word under the control of a serial clock
input, SCLK. The input shift register consists of an 8-bit address/
command byte, a 16-bit data-word, and an optional 8-bit CRC,
as shown in Table 13 and Table 14.
The address/command byte decoding is described in Table 12.
Table 12. Address/Command Byte Functions
Address/Command Byte Function
00000001 Write to DAC register
00000010 Write to control register
Address/Command Byte Function
00000011 Write to offset adjust register
00000100 Write to gain adjust register
00000101
Load DAC
00000110 Force alarm current
00000111
Reset (it is recommended to wait
50 µs after a device reset before
writing the next command)
00001000
Initiate V
LOOP
/temperature
measurement
00001001 No operation
10000001 Read DAC register
10000010 Read control register
10000011 Read offset adjust register
10000100
Read gain adjust register
10000101 Read fault register
The 16 bits of the data-word written following a load DAC, force
alarm current, reset, initiate V
LOOP
/temperature measurement,
or no operation command byte are don’t cares (see Table 13 and
Table 14).
REGISTER READBACK
To re ad back a register, Bit D11 of the control register must be set
to Logic 1 to disable the automatic readback of the fault register.
The 16 bits of the data-word written following a read command
are don’t cares (see Tabl e 13 and Table 14).
The register data addressed by the read command is clocked out
of SDO on the subsequent write command (see Figure 3).
Table 13. Input Shift Register
MSB LSB
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Address/command byte Data-word
Table 14. Input Shift Register with CRC
MSB LSB
D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Address/command byte Data-word CRC