Datasheet

Data Sheet AD5421
Rev. G | Page 25 of 36
Figure 48 shows a digitally controlled full-scale step and the
resulting filter output. In Figure 48, it can be seen that the peak
amplitude of the filter output signal is less than the required
150 mV, and the transition time is approximately 30 ms.
12
10
8
6
4
2
0
150
–150
–100
–50
0
50
100
–50 –30 –10 10 30 50
VOLTAGE ACROSS 500Ω LOAD RESISTOR (V)
OUTPUT OF HART DIGITAL FILTER (mV)
HCF_TOOL-31
TIME (ms)
09128-060
Figure 48. Digitally Controlled Full-Scale Step and Resulting HART Digital
Filter Output Signal
Figure 49 shows the circuit diagram for this measurement. The
47 nF and 168 nF capacitor values for C
HART
and C
SLEW
provide
adequate filtering of the digital steps, ensuring that they do not
cause interference.
09128-061
R
L
LOOP–
COMC
IN
REG
IN
V
LOOP
AD5421
FROM HART MODEM
47nF168nF
Figure 49. Circuit Diagram for Figure 48