Datasheet
AD5421 Data Sheet
Rev. G | Page 12 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDO
SCLK
SYNC
FAULT
LDAC
SDIN
IODV
DD
REG
IN
DRIVE
V
LOOP
R
EXT1
R
EXT2
LOOP–
DV
DD
ALARM_CURRENT_DIRECTION
R
INT
/R
EXT
COM
COM
RANGE1
RANGE0
C
IN
REFOUT1
REFOUT2
REG_SEL1
REG_SEL2
REG_SEL0
REFIN
REG
OUT
TOP VIEW
(Not to Scale)
AD5421
NOTES
1. THE EXPOSED PADDLE SHOULD BE CONNECTED TO THE SAME
POTENTIAL AS THE COM PIN AND TO A COPPER PLANE FOR
OPTIMUM THERMAL PERFORMANCE.
09128-004
Figure 5. TSSOP Pin Configuration
09128-100
PIN 1
INDICATOR
1
SDIN
2LDAC
3
FAULT
4
COM
5DV
DD
6
ALARM CURRENT DIRECTION
7R
INT
/R
EXT
8RANGE 0
24 V
LOOP
23 LOOP–
22 R
EXT2
21 R
EXT1
20 C
IN
19 REFOUT1
18 REFOUT2
17 REFIN
9
RANGE 1
10
COM
11
COM
12
NC
13
REG_SEL2
14
REG_SEL1
15
REG_SEL0
16
NC
32
SYNC
31
SCLK
30
SDO
29
IODV
DD
28
REG
OUT
27
REG
IN
26
DRIVE
25
NC
AD5421
TOP VIEW
(Not to Scale)
NOTES
1. NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PADDLE SHOULD BE CONNECTED TO THE
SAME POTENTIAL AS THE COM PIN AND TO A COPPER
PLANE FOR OPTIMUM THERMAL PERFORMANCE.
Figure 6. LFCSP Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic Description TSSOP LFCSP
1 29 IODV
DD
Digital Interface Supply Pin. Digital thresholds are referenced to the voltage applied to this pin. A
voltage from 1.71 V to 5.5 V can be applied to this pin.
2 30 SDO
Serial Data Output. Used to clock data from the input shift register. Data is clocked out on the
rising edge of SCLK and is valid on the falling edge of SCLK.
3 31 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of SCLK. This
input operates at clock speeds up to 30 MHz.
4 32
SYNC Frame Synchronization Input, Active Low. This is the frame synchronization signal for the serial
interface. When
SYNC is low, data is transferred on the falling edge of SCLK. The input shift
register data is latched on the rising edge of SYNC.
5 1 SDIN Serial Data Input. Data must be valid on the falling edge of SCLK.
6 2
LDAC Load DAC Input, Active Low. This pin is used to update the DAC register and, consequently, the
output current. If
LDAC is tied permanently low, the DAC register is updated on the rising edge
of
SYNC. If LDAC is held high during the write cycle, the input register is updated, but the output
update is delayed until the falling edge of
LDAC. The LDAC pin should not be left unconnected.
7
3
FAULT
Fault Alert Output Pin, Active High. This pin is asserted high when a fault is detected. Detectable
faults are loss of SPI interface control, communication error (PEC), loop current out of range,
insufficient loop voltage, and overtemperature. For more information, see the Fault Alerts
section.
8 5 DV
DD
3.3 V Digital Power Supply Output. This pin should be decoupled to COM with 100 nF and 4.7 µF
capacitors.
9 6
ALARM_
CURRENT_
DIRECTION
Alarm Current Direction Select. This pin is used to select whether the alarm current is upscale
(22.8 mA/24 mA) or downscale (3.2 mA). Connecting this pin to DV
DD
selects an upscale alarm
current (22.8 mA/24 mA); connecting this pin to COM selects a downscale alarm current (3.2 mA).
For more information, see the Power-On Default section.
10 7 R
INT
/R
EXT
Current Setting Resistor Select. When this pin is connected to DV
DD
, the internal current setting
resistor is selected. When this pin is connected to COM, the external current setting resistor is
selected. An external resistor can be connected between the R
EXT1
and R
EXT2
pins.
11, 12 8, 10
RANGE0,
RANGE1
Digital Input Pins. These two pins select the loop current range (see the Loop Current Range
Selection section).