Datasheet
Data Sheet AD5410/AD5420
Rev. F | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
12
11
DV
CC
FAULT
GND
LATCH
CLEAR
GND
GND
SCLK
SDIN
GND
GND
SDO
20
21
22
23
24
19
18
17
16
15
14
13
NC
CAP2
CAP1
R3
SENSE
NOTES
1. NC = NO CONNECT.
2. GROUND REFERENCE CONNECTION. IT IS RECOMMENDED THAT THE
EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR
ENHANCED THERMAL PERFORMANCE.
I
OUT
BOOST
NC
DV
CC
SELECT
R
SET
REFOUT
REFIN
AV
DD
AD5410/
AD5420
TOP VIEW
(Not to Scale)
07027-005
Figure 5. TSSOP Pin Configuration
07027-053
PIN 1
INDICATOR
1NC
2
3GND
4GND
5CLEAR
6LATCH
7SCLK
8SDIN
9SDO
10NC
23 DV
CC
SELECT
24
NC
25
R3
SENSE
26
I
OUT
27 BOOST
28 CAP1
29 CAP2
30 NC
22
NC
21 NC
1
1
NC
12
GND
13
GND
15
GND
17
REFOUT
16
R
SET
18
REFIN
19
NC
20
N
C
14
GND
33
NC
34
NC
35
NC
36
AV
DD
37
GND
38
NC
39
DV
CC
40
NC
32
NC
31
N
C
TOP VIEW
(Not to Scale)
AD5410/AD5420
FAULT
NOTES
1. NC = NO CONNECT.
2. GROUND REFERENCE CONNECTION. IT IS RECOMMENDED THAT THE
EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR
ENHANCED THERMAL PERFORMANCE.
Figure 6. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
TSSOP Pin No. LFCSP Pin No. Mnemonic Description
1, 4, 5, 12 3, 4, 14, 15, 37 GND These pins must be connected to ground.
2 39 DV
CC
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
3 2
FAU LT
Fault Alert. This pin is asserted low when an open circuit is detected between I
OUT
and
GND or an overtemperature is detected. The FAULT pin is an open-drain output and
must be connected to DV
CC
through a pull-up resistor (typically 10 kΩ).
6 5 CLEAR
Active High Input. Asserting this pin sets the output current to the zero-scale value,
which is either 0 mA or 4 mA, depending on the output range programmed, that is, 0 mA
to 20 mA, 0 mA to 24 mA, or 4 mA to 20 mA.
7 6 LATCH
Positive Edge Sensitive Latch. A rising edge parallel loads the input shift register data
into the relevant register. In the case of the data register, the output current is also
updated.
8 7 SCLK
Serial Clock Input. Data is clocked into the input shift register on the rising edge of
SCLK. This operates at clock speeds of up to 30 MHz.
9 8 SDIN Serial Data Input. Data must be valid on the rising edge of SCLK.
10 9 SDO
Serial Data Output. This pin is used to clock data from the device in daisy-chain or
readback mode. Data is clocked out on the falling edge of SCLK. See Figure 3 and
Figure 4.
11 12, 13 GND Ground Reference Pin.
13 16 R
SET
An external, precision, low drift 15 kΩ current setting resistor can be connected to this
pin to improve the overall performance of the device. See the Specifications and
AD5410/AD5420 Features sections.
14 17 REFOUT
Internal Reference Voltage Output. V
REFOUT
= 5 V ± 5 mV at T
A
= 25°C. Typical temperature
drift is 1.8 ppm/°C.
15 18 REFIN External Reference Voltage Input. V
REFIN
= 5 V ± 50 mV for specified performance.
16 23
DV
CC
SELECT
This pin, when connected to GND, disables the internal supply, and an external supply
must be connected to the DV
CC
pin. Leave this pin unconnected to enable the internal
supply. See the AD5410/AD5420 Features section.
17, 23
1, 10, 11, 19, 20,
21, 22, 24, 30,
31, 32, 33, 34,
35, 38, 40
NC Do not connect to these pins.