Datasheet

AD5410/AD5420 Data Sheet
Rev. F | Page 6 of 32
AC PERFORMANCE CHARACTERISTICS
AV
DD
= 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DV
CC
= 2.7 V to 5.5 V, R
LOAD
= 300 Ω; all specifications T
MIN
to T
MAX
, unless
otherwise noted.
Table 2.
Parameter
1
Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Current Settling Time
2
10 µs 16 mA step, to 0.1% FSR
40 µs 16 mA step, to 0.1% FSR, L = 1 mH
AC PSRR −75 dB 200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage
1
Guaranteed by design and characterization; not production tested.
2
Digital slew rate control feature disabled and CAP1 = CAP2 = open circuit.
TIMING CHARACTERISTICS
AV
DD
= 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DV
CC
= 2.7 V to 5.5 V, R
LOAD
= 300 Ω; all specifications T
MIN
to T
MAX
, unless
otherwise noted.
Table 3.
Parameter
1, 2, 3
Limit at T
MIN
, T
MAX
Unit Description
WRITE MODE
t
1
33 ns min SCLK cycle time
t
2
13 ns min SCLK low time
t
3
13 ns min SCLK high time
t
4
13
ns min
LATCH delay time
t
5
40 ns min LATCH high time
t
5
5 µs min LATCH high time after a write to the control register
t
6
5 ns min Data setup time
t
7
5 ns min Data hold time
t
8
40 ns min LATCH low time
t
9
20
ns min
CLEAR pulse width
t
10
5 µs max CLEAR activation time
READBACK MODE
t
11
90 ns min SCLK cycle time
t
12
40 ns min SCLK low time
t
13
40 ns min SCLK high time
t
14
13 ns min LATCH delay time
t
15
40 ns min LATCH high time
t
16
5
ns min
Data setup time
t
17
5 ns min Data hold time
t
18
40 ns min LATCH low time
t
19
35 ns max Serial output delay time (C
L SDO
= 50 pF)
4
t
20
35 ns max LATCH rising edge to SDO tristate
DAISY-CHAIN MODE
t
21
90 ns min SCLK cycle time
t
22
40 ns min SCLK low time
t
23
40 ns min SCLK high time
t
24
13 ns min LATCH delay time
t
25
40 ns min LATCH high time
t
26
5 ns min Data setup time
t
27
5 ns min Data hold time
t
28
40 ns min LATCH low time
t
29
35
ns max
Serial output delay time (C
L SDO
= 50 pF)
4
1
Guaranteed by characterization but not production tested.
2
All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of DV
CC
) and timed from a voltage level of 1.2 V.
3
See Figure 2, Figure 3, and Figure 4.
4
C
LSDO
= capacitive load on SDO output.