Datasheet

Data Sheet AD5410/AD5420
Rev. F | Page 23 of 32
HART COMMUNICATION
The AD5410/AD5420 contain a CAP2 pin, into which a HART
signal can be coupled. The HART signal appears on the current
output if the output is enabled. To achieve a 1 mA peak-to-peak
current, the signal amplitude at the CAP2 pin must be 48 mV
peak-to-peak. Assuming that the modem output amplitude is 500
mV peak-to-peak, its output must be attenuated by 500/48 = 10.42.
If this voltage is used, the current output should meet the HART
amplitude specifications. Figure 42 shows the recommended
circuit for attenuating and coupling in the HART signal.
HART MODEM
OUTPUT
C1
C2
CAP2
AVDD
07027-200
Figure 42. Coupling HART Signal
In determining the absolute values of the capacitors, ensure that
the FSK output from the modem is passed undistorted. Thus,
the bandwidth presented to the modem output signal must pass
1200 Hz and 2200 Hz frequencies. The recommended values
are C1 = 2.2 nF and C2 = 22 nF. Digitally controlling the slew
rate of the output is necessary to meet the analog rate of change
requirements for HART.
DIGITAL SLEW RATE CONTROL
The slew rate control feature of the AD5410/AD5420 allows the
user to control the rate at which the output current changes.
With the slew rate control feature disabled, the output current
changes at a rate of approximately 16 mA in 10 μs (see Figure 36).
This varies with load conditions. To reduce the slew rate, enable
the slew rate control feature. With the feature enabled via the
SREN bit of the control register (see Table 14), the output, instead
of slewing directly between two values, steps digitally at a rate
defined by two parameters accessible via the control register, as
shown in Table 14. The parameters are SR clock and SR step.
SR clock defines the rate at which the digital slew is updated,
SR step defines by how much the output value changes at each
update. Both parameters together define the rate of change of
the output current. Table 18 and Table 19 outline the range of
values for both the SR clock and SR step parameters. Figure 43
shows the output current changing for ramp times of 10 ms,
50 ms, and 100 ms.
Table 18. Slew Rate Update Clock Values
SR Clock Update Clock Frequency (Hz)
0000 257,730
0001 198,410
0010 152,440
0011 131,580
0100 115,740
0101 69,440
0110 37,590
0111 25,770
1000 20,160
1001 16,030
1010 10,290
1011 8280
1100 6900
1101 5530
1110 4240
1111 3300
Table 19. Slew Rate Step Size Options
SR Step AD5410 Step Size (LSB) AD5420 Step Size (LSB)
000 1/16 1
001 1/8 2
010 1/4 4
011 1/2 8
100 1 16
101 2 32
110 4 64
111 8 128
0
5
10
15
20
25
–10 0 10 20 30 40 50 60 70 80 90 100 110
OUTPUT CURRENT (mA)
TIME (ms)
T
A
= 25°C
AV
DD
= 24V
R
LOAD
= 300Ω
07027-139
10ms RAMP, SR CLOCK = 0x1, SR STEP = 0x5
50ms RAMP, SR CLOCK = 0xA, SR STEP = 0x7
100ms RAMP, SR CLOCK = 0x8, SR STEP = 0x5
Figure 43. Output Current Slewing Under Control of the Digital Slew Rate
Control Feature