Datasheet

AD5410/AD5420 Data Sheet
Rev. F | Page 20 of 32
POWER-ON STATE
Upon power-on of the AD5410/AD5420, the power-on reset
circuit ensures that all registers are loaded with zero code. As
such, the output is disabled (tristate). Also upon power-on,
internal calibration registers are read, and the data is applied to
internal calibration circuitry. For a reliable read operation, there
must be sufficient voltage on the AV
DD
supply when the read event
is triggered by the DV
CC
power supply powering up. Powering
up the DV
CC
supply after the AV
DD
supply ensures this. If DV
CC
and AV
DD
are powered up simultaneously or if the internal DV
CC
is enabled, the supplies should be powered up at a rate greater
than, typically, 500 V/sec or 24 V per 50 ms. If this cannot be
achieved, simply issue a reset command to the AD5410/AD5420
after power-on. This performs a power-on reset event, reading
the calibration registers and ensuring specified operation of the
AD5410/AD5420.
TRANSFER FUNCTION
For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA
current output ranges, the output current is respectively
expressed as
DI
N
OUT








2
mA20
DI
N
OUT








2
mA24
mA4
2
mA16







 DI
N
OUT
where:
D is the decimal equivalent of the code loaded to the DAC.
N is the bit resolution of the DAC.
DATA REGISTER
The data register is addressed by setting the address byte of the
input shift register to 0x01. The data to be written to the data
register is entered in Position DB15 to Position DB4 for the
AD5410 and in Position DB15 to Position DB0 for the AD5420,
as shown in Tabl e 12 and Table 13, resp ectively.
CONTROL REGISTER
The control register is addressed by setting the address byte of
the input shift register to 0x55. The data to be written to the
control register is entered in Position DB15 to Position DB0,
as shown in Table 14. The control register bit functions are
described in Table 10.
Table 10. Control Register Bit Functions
Bit Description
REXT
Setting this bit selects the external current setting
resistor. See the AD5410/AD5420 Features section
for further details. When using an external current
setting resistor, it is recommended to only set REXT
when also setting the OUTEN bit. Alternately, REXT
can be set before the OUTEN bit is set, but the range
(see Table 11) must be changed on the write in which
the output is enabled. See Figure 40 for best practice.
OUTEN
Output enable. This bit must be set to enable the
output.
SR Clock
Digital slew rate control. See the AD5410/AD5420
Features section.
SR Step
Digital slew rate control. See the AD5410/AD5420
Features section.
SREN Digital slew rate control enable.
DCEN Daisy-chain enable.
R2, R1, R0 Output range select. See Table 11.
Table 11. Output Range Options
R2 R1 R0 Output Range Selected
1 0 1 4 mA to 20 mA current range
1 1 0 0 mA to 20 mA current range
1 1 1 0 mA to 24 mA current range
Table 12. Programming the AD5410 Data Register
MSB LSB
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
12-bit data-word X
1
X
1
X
1
X
1
1
X = don’t care.
Table 13. Programming the AD5420 Data Register
MSB LSB
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
16-bit data-word
Table 14. Programming the Control Register
MSB LSB
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 REXT OUTEN SR clock SR step SREN DCEN R2 R1 R0