Datasheet

AD5415 Data Sheet
Rev. E | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD5415
TOP VIEW
(Not to Scale)
SDIN
SCLK
GND
V
REF
A
I
OUT
1A
I
OUT
2A
R
FB
A
R1A
R3A
R2_3A
R2A
CLR
V
DD
V
REF
B
I
OUT
1B
I
OUT
2B
R
FB
B
R1B
R3B
R2_3B
R2B
LDAC
SDO
SYNC
04461-005
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 I
OUT
1A DAC A Current Output.
2 I
OUT
2A DAC A Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
3 R
FB
A DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to an external amplifier
output.
4 to 7 R1A, R2A,
R2_3A, R3A
DAC A 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with
minimum external components.
8 V
REF
A DAC A Reference Voltage Input Pin.
9 GND Ground Pin.
10
LDAC
Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is
asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an
automatic or synchronous update mode is selected, whereby the DAC is updated on the 16th clock falling edge
when the device is in standalone mode, or on the rising edge of
SYNC
when in daisy-chain mode.
11 SCLK Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
input.
Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into
the shift register on the rising edge of SCLK.
12 SDIN Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, on power-up data is clocked into the shift register on the falling edge of SCLK. The control bits allow the
user to change the active edge to the rising edge.
13 SDO Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and clocked out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes
the DAC register contents available for readback on the SDO pin; they are clocked out on the next 16 opposite
clock edges to the active clock edge.
14
SYNC
Active Low Control Input. This pin provides the frame synchronization signal for the input data. When
SYNC
goes
low, it powers on the SCLK and SDIN buffers, and the input shift register is enabled. Data is loaded into the shift
register on the active edge of the subsequent clocks. In standalone mode, the serial interface counts the clocks,
and data is latched into the shift register on the 16th active clock edge.
15
CLR
Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the user
to enable the hardware
CLR
pin as a clear to zero scale or midscale as required.
16 V
DD
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
17 V
REF
B DAC B Reference Voltage Input Pin.
18 to 21 R3B, R2_3B,
R2B, R1B
DAC B 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with
a minimum of external components.
22 R
FB
B DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external
amplifier output.
23 I
OUT
2B DAC B Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
24 I
OUT
1B DAC B Current Output.