Datasheet

AD5405
Rev. B | Page 5 of 24
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. V
DD
= 2.5 V to 5.5 V,
V
REF
= 10 V, I
OUT
2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1
Limit at T
MIN
, T
MAX
Unit Conditions/Comments
Write Mode
t
1
0 ns min
R/W
-to-CS setup time
t
2
0 ns min
R/W
-to-CS hold time
t
3
10 ns min
CS
low time
t
4
10 ns min Address setup time
t
5
0 ns min Address hold time
t
6
6 ns min Data setup time
t
7
0 ns min Data hold time
t
8
5 ns min
R/W
high to CS low
t
9
7 ns min
CS
min high time
t
14
10 ns typ
CS
rising-to-LDAC falling time
t
15
12 ns typ
LDAC
pulse width
t
16
10 ns typ
CS
rising-to-LDAC rising time
t
17
10 ns typ
LDAC
falling-to-CS rising time
Data Readback Mode
t
10
0 ns typ Address setup time
t
11
0 ns typ Address hold time
t
12
5 ns typ Data access time
35 ns max
t
13
5 ns typ Bus relinquish time
10 ns max
Update Rate 21.3 MSPS
Consists of CS
min high time, CS low time, and output voltage settling time
1
Guaranteed by design and characterization, not subject to production test.
04463-002
t
7
DATA VALID
t
6
t
2
CS
R/W
DATA
t
1
t
2
t
13
t
12
t
3
t
8
t
9
DACA/DACB
t
4
t
5
t
11
t
10
LDAC
2
LDAC
1
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
t
16
t
14
t
15
t
17
DATA VALID
Figure 2. Timing Diagram
I
OL
200 μ A
I
OH
200 μ A
C
L
50pF
TO
OUTPUT
PIN
V
OH (MIN)
+ V
OL (MAX)
2
04463-003
Figure 3. Load Circuit for Data Timing Specifications