Datasheet

AD539
Rev. B | Page 13 of 20
Table 4. Summary of Operating Conditions and
Performance for the AD539 When Used with Various
External Op Amp Output Amplifiers
Operating Conditions AD711
1
LH0032
1
Op Amp Supply Voltages ±15 V ±10 V
Op Amp Compensation Capacitor None 1 pF to 5 pF
Feedback Capacitor, C
F
None 1 pF to 4 pF
−3 dB Bandwidth, V
X
= 1 V 900 kHz 25 MHz
Load Capacitance <1 nF <10 pF
HF Feedthrough
V
X
= −0.01 V, f = 5 MHz N/A −70 dB
RMS Output Noise
V
X
= 1 V, BW 10 Hz to10 kHz 50 μV 30 μV
V
X
= 1 V, BW 10 Hz to 5 MHz 120 μV 500 μV
1
For the circuit of Figure 20.
In all cases, 0.47 μF ceramic supply decoupling capacitors were
used at each IC pin, the AD539 supplies were ±5 V, and the
control compensation capacitor C
C
was 3 nF.
Minimal Wideband Configurations
The maximum bandwidth can be achieved using the AD539
with simple resistive loads to convert the output currents to
voltages. These currents (nominally ±1 mA FS, ±2.25 mA peak,
into short-circuit loads) are shunted by their source resistance
of 1.25 kΩ (each channel). Calculations of load power and
effective scaling-voltage must allow for this shunting effect
when using resistive loads. The output power is quite low in this
mode, and the device behaves more like a voltage-controlled
attenuator than a classical multiplier. The matching of gain and
phase between the two channels is excellent. From dc to 10 MHz,
the gains are typically within ±0.025 dB (measured using preci-
sion 50 Ω load resistors) and the phase difference within ±0.1°.
For a given load resistance, the output power can be quadrupled
by using both channels in parallel, as shown in Figure 21. The
small signal silicon diode, D, connected between ground and
BASE COMMON (Pin 12 and Pin 13) provides extra voltage
compliance at the output nodes in the negative direction (to
−1 V at 25°C); it is not required if the output swing does not
exceed −300 mV. Tabl e 5 compares performance for various
load resistances, using this configuration.
09679-021
1
2
3
4
16
15
14
13
5 12
6 11
7 10
8 9
AD539
V
X
V
Y1
V
Y2
HF COMP
+V
S
–V
S
INPUT
COMMON
OUTPUT
COMMON
BASE
COMMON
W1
Z1
CHAN1
OUTPUT
CHAN2
OUTPUT
Z2
W2
C
C
= 3nF
V
X
NC
NC
NC
NC
0.47µF
+V
S
D*
R
L
–V
S
V
Y
V
W
=
V
X
V
Y
V
U
REQUIRED IF LOAD
RESISTANCE >300Ω
*
Figure 21. Minimal Single-Channel Multiplier
(16-Lead SBDIP and PDIP Shown)
Figure 9 shows the high frequency response for Figure 21 with
the AD539 in a carefully shielded 50 Ω test environment; the
test system response was first characterized and this
background removed by digital signal processing to show the
inherent circuit response.
In many applications phase linearity over frequency is important.
Figure 10 shows the deviation from an ideal linear-phase response
for a typical AD539 over the frequency range dc to 10 MHz, for
V
X
= 3 V; the peak deviation is slightly more than 1°. Differen-
tial phase linearity (the stability of phase over the signal window
at a fixed frequency) is shown in Figure 11 for f = 3.579 MHz
and various values of V
X
. The most rapid variation occurs for
V
Y
above 1 V; in applications where this characteristic is critical,
it is recommended that a ground-referenced, negative-going
signal be used.
Table 5. Summary of Performance for Minimal Configuration
Load Resistance 50 Ω 75 Ω 100 Ω 150 Ω 600 Ω Open Circuit
FS Output Voltage
DC ±92.6 mV ±134 mV ±172 mV ±242 mV ±612 mV ±1 V
AC (RMS) 65.5 mV rms 94.7 mV rms 122 mV rms 171 mV rms 433 mV rms Note
1
FS Output 0.086 mW 0.12 mW 0.15 mW 0.195 mW 0.312 mW N/A
2
Power in Load −10.5 dBm −9.2 dBm −8.3 dBm −7.1 dBm −5.05 dBm N/A
Peak Output Voltage
DC ±210 mV ±300 mV ±388 mV ±544 mV ±1 mV ±1 V
AC (RMS) 148 mV rms 212 mV rms 274 mV rms 385 mV rms Note
1
Note
1
Peak Output 0.44 mW 0.6 mW 0.75 mW 1 mW ±1 V ±1 V
Power in Load −7 dBm −4.4 dBm −2.5 dBm 0 dBm Note
1
Note
1
Effective Scaling Voltage, V
U
’ 67.5 V 46.7 V 36.3 V 25.8 V 10.2 V 5 V
1
Peak negative voltage swing limited by output compliance.
2
N/A means not applicable.