Datasheet
AD5398
Rev. B | Page 4 of 16
AC SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance R
L
= 25 Ω connected to V
DD
, unless otherwise noted.
Table 2.
B Version
1, 2
Parameter Min Typ Max Unit Test Conditions/Comments
Output Current Settling Time 250 μs
V
DD
= 5 V, R
L
= 25 Ω, L
L
= 680 μH
¼ scale to ¾ scale change (0x100 to 0x300)
Slew Rate 0.3 mA/μs
Major Code Change Glitch Impulse 0.15 nA-s 1 LSB change around major carry
Digital Feedthrough
3
0.06 nA-s
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design and characterization; not production tested.
3
See the Terminology section.
TIMING SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
B Version
Parameter
1
Limit at T
MIN
, T
MAX
Unit
Description
f
SCL
400 kHz max SCL clock frequency
t
1
2.5 μs min SCL cycle time
t
2
0.6 μs min t
HIGH
, SCL high time
t
3
1.3 μs min t
LOW
, SCL low time
t
4
0.6 μs min t
HD, STA
, start/repeated start condition hold time
t
5
100 ns min t
SU, DAT
, data setup time
t
6
2
0.9 μs max t
HD, DAT
, data hold time
0 μs min
t
7
0.6 μs min t
SU, STA
, setup time for repeated start
t
8
0.6 μs min t
SU, STO
, stop condition setup time
t
9
1.3 μs min t
BUF
, bus free time between a stop condition and a start condition
t
10
300 ns max t
R,
rise time of both SCL and SDA when receiving
0 ns min May be CMOS driven
t
11
250 ns max t
F
, fall time of SDA when receiving
300 ns max t
F
, fall time of both SCL and SDA when transmitting
20 + 0.1 C
b
3
ns min
C
b
400 pF max Capacitive load for each bus line
1
Guaranteed by design and characterization; not production tested.
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal) in order to bridge the undefined region of SCL’s
falling edge.
3
C
b
is the total capacitance of one bus line in pF. t
R
and t
F
are measured between 0.3 V
DD
and 0.7 V
DD.
05034-002
SDA
t
9
SCL
t
3
t
10
t
11
t
4
t
4
t
6
t
2
t
5
t
7
t
1
t
8
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram