Datasheet

AD5398
Rev. B | Page 3 of 16
SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance R
L
= 25 Ω connected to V
DD
; all specifications T
MIN
to T
MAX
,
unless otherwise noted.
Table 1.
B Version
1
Parameter Min Typ Max Unit Test Conditions/Comments
DC PERFORMANCE
V
DD
= 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V with
reduced performance
Resolution 10 Bits 117 μA/LSB
Relative Accuracy
2
±1.5 ±4 LSB
Differential Nonlinearity
2, 3
±1 LSB Guaranteed monotonic over all codes
Zero Code Error
2, 4
0 1 5 mA All 0s loaded to DAC
Offset Error @ Code 16
2
0.5 mA
Gain Error
2
±0.6 % of FSR @ 25°C
Offset Error Drift
4, 5
10 μA/°C
Gain Error Drift
2, 5
±0.2 ±0.5 LSB/°C
OUTPUT CHARACTERISTICS
Minimum Sink Current
4
3 mA
Maximum Sink Current 120 mA
V
DD
= 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V but
specified maximum sink current might not be achieved
Output Current During PD 80 nA PD = 1
Output Compliance
5
0.6 V
DD
V
Output voltage range over which max sink current is
available
Power-Up Time 20 μs To 10% of FS, coming out of power-down mode; V
DD
= 5 V
LOGIC INPUTS (PD)
5
Input Current ±1 μA
Input Low Voltage, V
INL
0.8 V V
DD
= 2.7 V to 5.5 V
Input High Voltage, V
INH
0.7 V
DD
V V
DD
= 2.7 V to 5.5 V
Pin Capacitance 3 pF
LOGIC INPUTS (SCL, SDA)
5
Input Low Voltage, V
INL
−0.3 0.3 V
DD
V
Input High Voltage, V
INH
0.7 V
DD
V
DD
+ 0.3
V
Input Leakage Current, I
IN
±1 μA V
IN
= 0 V to V
DD
Input Hysteresis, V
HYST
0.05 V
DD
V
Digital Input Capacitance, C
IN
6 pF
Glitch Rejection
6
50 ns Pulse width of spike suppressed
POWER REQUIREMENTS
V
DD
2.7 5.5 V
I
DD
(Normal Mode) I
DD
specification is valid for all DAC codes
V
DD
= 2.7 V to 5.5 V 2.5 4 mA V
IH
= V
DD
, V
IL
= GND, V
DD
= 5.5 V
V
DD
= 2.7 V to 4.5 V 2.3 3 mA V
IH
= V
DD
, V
IL
= GND, V
DD
= 4.5 V
I
DD
(Power-Down Mode) 0.5 1 μA V
IH
= V
DD
, V
IL
= GND
1
Temperature range is as follows: B Version: −40°C to +85°C.
2
See the Terminology section.
3
Linearity is tested using a reduced code range: Codes 32 to 1023.
4
To achieve near zero output current, use the power-down feature.
5
Guaranteed by design and characterization; not production tested.
6
Input filtering on both the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.