Datasheet

AD5390/AD5391/AD5392 Data Sheet
Rev. E | Page 36 of 44
AD539x to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit = 0. This is done
by writing to the synchronous serial port control register
(SSPCON)—see the PIC16/17 Microcontroller User Manual.
In Figure 38, I/O port RA1 is used to pulse
SYNC
and enable
the serial port of the AD539x. This microcontroller transfers
only eight bits of data during each serial transfer operation;
therefore, three consecutive read/write operations are needed,
depending on the mode. Figure 38 shows the connection
diagram.
DV
DD
PIC16C6x/7x
AD539x
RESET
SDO
SDI/RC4
DIN
SDO/RC5
SCLK
SCK/RC3
RA1
SYNC
SPI/I
2
C
03773-027
Figure 38. AD539x to PIC16C6x/7x Interface
AD539x to 8051
The AD539x requires a clock synchronized to the serial data.
The 8051 serial interface must, therefore, be operated in Mode 0.
In this mode, serial data enters and exits through RxD and a
shift clock is output on TxD. Figure 39 shows how the 8051 is
connected to the AD539x. Because the AD539x shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD539x
requires its data with the MSB first. Because the 8051 outputs
the LSB first, the transmit routine must take this into account.
DV
DD
DV
DD
8xC51
SDO
DIN
AD539x
RESET
RxD
SCLKTxD
P1.1
SYNC
SPI/I
2
C
0
3773-028
Figure 39. AD539x to 8051 Interface
AD539x to ADSP2101
Figure 40 shows a serial interface between the AD539x and
the ADSP2101. The ADSP2101 should be set up to operate in
the SPORT transmit alternate framing mode. The ADSP2101
SPORT is programmed through the SPORT control register and
should be configured as follows: internal clock operation, active
low framing, and 16-bit word length. Transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled.
DV
DD
ADSP2101
AD539x
RESET
DINDT
SDODR
SCLKSCK
TFS
RFS
SYNC
SPI/I
2
C
0
3773-029
Figure 40. AD539x to ADSP2101 Interface