Datasheet

AD5390/AD5391/AD5392 Data Sheet
Rev. E | Page 30 of 44
2-BYTE MODE
The 2-byte mode lets the user update channels sequentially
following initialization of this mode. The device address byte is
required only once and the address pointer is configured for
autoincrement or burst mode.
The user must begin with an address byte (R/
W
= 0), after
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. The address byte is followed by a specific
pointer byte (0xFF), which initiates the burst mode of opera-
tion. The address pointer initializes to Channel 0 and the data
following the pointer is loaded to Channel 0. The address
pointer automatically increments to the next address.
The REG0 and REG1 bits in the data byte determine the register
to be updated. In this mode, following the initialization, only
the two data bytes are required to update a channel. The
channel address automatically increments from Address 0 to
the final address and then returns to the normal 3-byte mode
of operation. This mode allows transmission of data to all
channels in one block and reduces the software overhead in
configuring all channels. A STOP condition at any time exits
this mode. Toggle mode of operation is not supported in
2-byte mode. Figure 36 shows a typical configuration.
REG0 MSB MSBLSB LSBREG1
1 0 0 A7 = 1 A6 = 1 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 11 1 AD1 AD0 R/W
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
START
CONDITION
BY
MASTER
ACK
BY
CONVERTER
ACK
BY
CONVERTER
ADDRESS BYTE POINTER BYTE
CHANNEL 1 DATA
CHANNEL 0 DATA
CHANNEL N DATA FOLLOWED BY STOP
MSB
ACK
BY
CONVERTER
ACK
BY
CONVERTER
MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE
REG0 MSB MSBLSB LSBREG1
ACK
BY
CONVERTER
ACK
BY
CONVERTER
MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE
REG0 MSB MSBLSB LSBREG1
ACK
BY
CONVERTER
ACK
BY
CONVERTER
STOP
CONDITION
BY
MASTER
MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE
03773-025
Figure 36. 2-Byte Mode I
2
C Write Operation