Datasheet

Data Sheet AD5390/AD5391/AD5392
Rev. E | Page 17 of 44
Mnemonic Function
PD Power-Down (level-sensitive, active high). Used to place the device in low power mode, in which the device consumes
1 µA analog current and 20 µA digital current. In power-down mode, all internal analog circuitry is placed in low power
mode; the analog output is configured as high impedance outputs or provides a 100 kΩ load to ground, depending on
how the power-down mode is configured. The serial interface remains active during power-down.
SPI/
I
2
C
Interface Select Input Pin. When this input is low, I
2
C mode is selected. When this input is high, SPI mode is selected.
SCLK/SCL Interface Clock Input Pin. In SPI-compatible serial interface mode, this pin acts as a serial clock input. It operates at clock
speeds up to 50 MHz.
I
2
C mode: In I
2
C mode, this pin performs the SCL function, clocking data into the device. Data transfer rate in I
2
C mode is
compatible with both 100 kHz and 400 kHz operating modes.
DIN/SDA Interface Data Input Pin.
SPI/
I
2
C
= 1: This pin acts as the serial data input. Data must be valid on the falling edge of SCLK.
SPI/
I
2
C
= 0, I
2
C mode: In I
2
C mode, this pin is the serial data pin (SDA) operating as an open drain input/output.
TEST Test pin (AD5392 only). This pin is used for production testing. For normal operation, this pin should not be connected.
NC No Connect. These pins have no internal connection.
Exposed Pad
(LFCSP only)
This pad should be connected to the ground plane.