Datasheet

Data Sheet AD5390/AD5391/AD5392
Rev. E | Page 25 of 44
INTERFACES
The AD5390/AD5391/AD5392 contain a serial interface that
can be programmed to be DSP-, SPI-, and MICROWIRE-
compatible, or I
2
C-compatible. The SPI/
I
2
C
pin is used to select
the interface mode.
To minimize both the power consumption of the device and the
on-chip digital noise, the interface fully powers up only when the
device is being written to, that is, on the falling edge of
SYNC
.
DSP-, SPI-, AND MICROWIRE-COMPATIBLE SERIAL
INTERFACE
The serial interface can be operated with a minimum of three
wires in standalone mode or four wires in daisy-chain mode.
Daisy-chaining allows many devices to be cascaded together to
increase system channel count. The SPI/
I
2
C
pin is tied to a
Logic 1 pin to configure this mode of operation. The serial
interface control pins are described in Table 17.
Table 17. Serial Interface Control Pins
Pin Description
SYNC
, DIN, SCLK Standard 3-wire interface pins.
DCEN Selects standalone mode or daisy-chain mode.
SDO Data out pin for daisy-chain mode.
Figure 2 to Figure 4 show timing diagrams for a serial write to
the AD5390/AD5391/AD5392 in both standalone and daisy-
chain mode. The 24-bit data-word format for the serial interface
is shown in Table 18 to Table 20. Descriptions of the bits follow
in Table 21.
Table 18. AD5390 16-Channel, 14-Bit DAC Serial Input Register Configuration
MSB LSB
A
/B R/
W
0 0 A3 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Table 19. AD5391 16-Channel, 12-Bit DAC Serial Input Register Configuration
MSB LSB
A
/B R/
W
0 0 A3 A2 A1 A0 REG1 REG0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X
Table 20. AD5392 8-Channel, 14-Bit DAC Serial Input Register Configuration
MSB LSB
A
/B R/
W
0 0 0 A2 A1 A0 REG1 REG0 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Table 21. Serial Input Register Configuration Bit Descriptions
Bit Description
A
/B When toggle mode is enabled, this bit selects whether the data write is to the A or B register. With toggle mode disabled, this
bit should be set to zero to select the A data register.
R/
W
The read or write control bit.
A3 to A0
Used to address the input channels.
REG1 and
REG0
Select the register to which data is written, as outlined in Table 10.
DB13 to
DB0
Contain the input data-word.
X Don’t care condition.