Datasheet

Data Sheet AD5390/AD5391/AD5392
Rev. E | Page 13 of 44
I
2
C SERIAL INTERFACE
DV
DD
= 2.7 V to 5.5 V; AV
DD
= 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 7. I
2
C Serial Interface
1
Parameter
2
Limit at T
MIN
, T
MAX
Unit Description
F
SCL
400 kHz max SCL clock frequency
t
1
2.5 µs min SCL cycle time
t
2
0.6 µs min t
HIGH
, SCL high time
t
3
1.3 µs min t
LOW
, SCL low time
t
4
0.6 µs min t
HD
,
STA
, start/repeated start condition hold time
t
5
100 ns min t
SU
,
DAT
, data setup time
t
6
3
0.9 µs max t
HD
,
DAT
data hold time
0 µs min t
HD
,
DAT
data hold time
t
7
0.6
µs min
t
SU
,
STA
setup time for repeated start
t
8
0.6 µs min t
SU
,
STO
stop condition setup time
t
9
1.3 µs min t
BUF
, bus free time between a stop and a start condition
t
10
300 ns max t
F
, fall time of SDA when transmitting
0 ns min t
R
, rise time of SCL and SDA when receiving (CMOS-compatible)
t
11
300 ns max t
F
, fall time of SDA when transmitting
0 ns min t
F
, fall time of SDA when receiving (CMOS-compatible)
300 ns max t
F
, fall time of SCL and SDA when receiving
20 + 0.1 C
B
ns min t
F
, fall time of SCL and SDA when transmitting
C
B
4
400 pF max Capacitive load for each bus line
1
Guaranteed by design and characterization, not production tested.
2
See Figure 6.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
MIN of the SCL signal) to bridge the undefined region of SCL’s falling edge.
4
C
B
is the total capacitance of one bus line in pF; t
R
and t
F
measured between 0.3 DV
DD
and 0.7 DV
DD
.
SCL
SDA
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t
9
t
3
t
10
t
11
t
4
t
4
t
6
t
2
t
5
t
7
t
8
t
1
03773-007
Figure 6. I
2
C Interface Timing Diagram