Datasheet

AD5390/AD5391/AD5392 Data Sheet
Rev. E | Page 12 of 44
t
1
24 24
1
2
t
3
t
2
t
5
t
7
t
4
t
6
t
8
t
9
t
10
t
13
t
12
t
14
t
17
t
13
t
15
t
18
t
19
t
16
VOUT 2
CLR
VOUT
1
LDAC ACTIVE DURING BUSY
2
LDAC ACTIVE DURING BUSY
SCLK
SYNC
DIN
BUSY
LDAC
1
LDAC
2
VOUT 1
DB0
DB23
t
17
t
11
03773-005
Figure 3. Serial Interface Timing Diagram (Standalone Mode)
SELECTED REGISTER DATA
CLOCKED OUT
DB23 DB0
DB23' DB0
48
NOP CONDITION
UNDEFINED
SDO
SCLK
SYNC
DIN
DB23
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
24
t
7A
03773-006
Figure 4. Serial Interface Timing Diagram (Data Readback Mode)
I
OL
200µA
200µA
50pF
TO
OUTPUT
PIN
I
OH
C
L
V
OH (MIN)
OR
V
OL (MAX)
03773-003
Figure 5. Load Circuit for Digital Output Timing