Datasheet

Data Sheet AD5390/AD5391/AD5392
Rev. E | Page 11 of 44
TIMING CHARACTERISTICS
SERIAL SPI-, QSPI-, MICROWIRE-, AND DSP-COMPATIBLE INTERFACE
DV
DD
= 2 V to 5.5 V; AV
DD
= 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 6. 3-Wire Serial Interface
1
Parameter
2, 3
Limit at T
MIN
, T
MAX
Unit Description
t
1
33 ns min SCLK cycle time
t
2
13 ns min SCLK high time
t
3
13 ns min SCLK low time
t
4
13 ns min
SYNC
falling edge to SCLK falling edge setup time
t
5
4
13 ns min 24
th
SCLK falling edge to
SYNC
falling edge
t
6
4
33 ns min Minimum
SYNC
low time
t
7
10 ns min Minimum
SYNC
high time
t
7
50 ns min Minimum
SYNC
high time in readback mode
t
8
5 ns min Data setup time
t
9
4.5 ns min Data hold time
t
10
4
30 ns max 24
th
SCLK falling edge to
BUSY
falling edge
t
11
670
ns max
BUSY
pulse width low (single channel update)
t
12
4
20 ns min 24
th
SCLK falling edge to
LDAC
falling edge
t
13
20 ns min
LDAC
pulse width low
t
14
2 μs max
BUSY
rising edge to DAC output response time
t
15
0 ns min
BUSY
rising edge to
LDAC
falling edge
t
16
100 ns min
LDAC
falling edge to DAC output response time
t
17
8 µs typ DAC output settling time, AD5390/AD5392
t
17
6 µs typ DAC output settling time, AD5391
t
18
20 ns min
CLR
pulse width low
t
19
40 µs max
CLR
pulse activation time
t
20
5
20 ns max SCLK rising edge to SDO valid
t
21
4
5
ns min
SCLK falling edge to
SYNC
rising edge
t
22
4
8 ns min
SYNC
rising edge to SCLK rising edge
t
23
4
20 ns min
SYNC
rising edge to
LDAC
falling edge
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.2 V.
3
See Figure 2, Figure 3, Figure 4, and Figure 5.
4
Standalone mode only.
5
Daisy-chain mode only.
SDO
SCLK
SYNC
DIN
LDAC
t
1
24 48
t
3
t
2
t
21
t
22
t
7
t
4
t
8
t
9
DB23 DB0 DB23
DB0
DB0
INPUT WORD FOR DAC N INPUT WORD FOR DAC N+1
UNDEFINED
INPUT WORD FOR DAC N
t
20
t
23
t
13
DB23
03773-002
Figure 2. Serial Interface Timing Diagram (Daisy-Chain Mode)