Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) LQFP 52

8-/16-Channel, 3 V/5 V, Serial Input,

Single-Supply, 12-/14-Bit Voltage Output

Data Sheet

AD5390/AD5391/AD5392

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

FEATURES

AD5390: 16-channel, 14-bit voltage output DAC

AD5391: 16-channel, 12-bit voltage output DAC

AD5392: 8-channel, 14-bit voltage output DAC

Guaranteed monotonic

INL

±1 LSB max (AD5391)

±3 LSB max (AD5390-5/AD5392-5)

±4 LSB max (AD5390-3/AD5392-3)

On-chip 1.25 V/2.5 V, 10 ppm/°C reference

Temperature range: −40°C to +85°C

Rail-to-rail output amplifier

Power-down mode

Package types

64-lead LFCSP (9 mm × 9 mm)

52-lead LQFP (10 mm × 10 mm)

User interfaces

Serial SPI-, QSPI-, MICROWIRE-, and DSP-compatible

(featuring data readback)

C-compatible interface

Integrated functions

channel monitor

simultaneous output update via

LDAC

clear function to user-programmable code

amplifier boost mode to optimize slew rate

user-programmable offset and gain adjust

toggle mode enables square wave generation

thermal monitor

Robust 6.5 kV HBM and 2 kV FICDM ESD rating

APPLICATIONS

Instrumentation and industrial control

Power amplifier control

Level setting (ATE)

Control systems

Microelectromechanical systems (MEMs)

Variable optical attenuators (VOAs)

Optical transceivers (MSA 300, XFP)

FUNCTIONAL BLOCK DIAGRAM

DAC 0

VOUT 0

DAC

REG

1414

DAC 1

VOUT 1

VOUT 2

VOUT 3

VOUT 4

VOUT 5

DAC

REG

1414

DAC 6

VOUT 6

DAC

REG

1414

DAC 7

VOUT 7

VOUT 8

VOUT 15

DAC

REG

m REG0

c REG0

1414

INPUT

REG

m REG1

c REG1

1414

INPUT

REG

m REG6

c REG6

1414

INPUT

REG

m REG7

c REG7

1414

INPUT

REG

STATE

MACHINE

AND

CONTROL

LOGIC

INTERFACE

CONTROL

LOGIC

DIN/SDA

DCEN/AD1

SPI/I

SCLK/SCL

SYNC/AD0

SDO

1.25V/2.5V

REFERENCE

AD5390

REFOUT/REFIN SIGNAL_GND (×2)REF_GNDDAC_GND (×2)

AGND (×2)AV

(×2)DGND (×3/×4)DV

(×3)

×2

LDAC

POWER-ON

RESET

BUSY

CLR

RESET

MON_IN1

MON_IN2

MON_OUT

0 V

MUX

03773-001

Figure 1.

Summary of content (44 pages)

PAGE 1
8-/16-Channel, 3 V/5 V, Serial Input, Single-Supply, 12-/14-Bit Voltage Output AD5390/AD5391/AD5392 Data Sheet FEATURES I2C-compatible interface Integrated functions channel monitor simultaneous output update via LDAC clear function to user-programmable code amplifier boost mode to optimize slew rate user-programmable offset and gain adjust toggle mode enables square wave generation thermal monitor Robust 6.
PAGE 2
AD5390/AD5391/AD5392 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 I2C Serial Interface ..................................................................... 27 Applications ....................................................................................... 1 I2C Write Operation ....................................................................... 28 Functional Block Diagram .................................
PAGE 3
Data Sheet AD5390/AD5391/AD5392 10/04—Rev. 0 to Rev. A Changes to Features .......................................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Table 3 ............................................................................ 6 Changes to Table 4 .............................................
PAGE 4
AD5390/AD5391/AD5392 Data Sheet GENERAL DESCRIPTION The AD5390/AD5391/AD5392 contain a 3-wire serial interface with interface speeds in excess of 30 MHz that are compatible with SPI®, QSPI™, MICROWIRE™, and DSP interface standards and an I2C-compatible interface supporting a 400 kHz data transfer rate. The AD5390/AD5391 are complete single-supply, 16-channel, 14-bit and 12-bit DACs, respectively. The AD5392 is a complete single-supply, 8-channel, 14-bit DAC.
PAGE 5
Data Sheet AD5390/AD5391/AD5392 SPECIFICATIONS AD5390-5/AD5391-5/AD5392-5 SPECIFICATIONS AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 2.5 V external. All specifications TMIN to TMAX, unless otherwise noted. Table 2.
PAGE 6
AD5390/AD5391/AD5392 Data Sheet AD5390-5 1 AD5392-51 AD5391-51 Unit Test Conditions/Comments 0.7 × DVDD 0.3 × DVDD ±1 0.05 × DVDD 8 50 0.7 × DVDD 0.3 × DVDD ±1 0.05 × DVDD 8 50 V min V max µA max V min pF typ ns max SMBus-compatible at DVDD < 3.6 V SMBus-compatible at DVDD < 3.6 V 0.4 DVDD − 1 0.4 DVDD − 0.5 ±1 5 0.4 DVDD − 1 0.4 DVDD − 0.5 ±1 5 V max V min V max V min µA max pF typ DVDD = 5 V ± 10%, sinking 200 µA DVDD = 5 V ± 10%, SDO only, sourcing 200 µA DVDD = 2.7 V to 3.
PAGE 7
Data Sheet AD5390/AD5391/AD5392 AD5390-5/AD5391-5/AD5392-5 AC CHARACTERISTICS AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. Table 3. Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time AD5390/AD5392 AD5391 Slew rate 2 Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough Output Noise (0.
PAGE 8
AD5390/AD5391/AD5392 Data Sheet AD5390-3/AD5391-3/AD5392-3 SPECIFICATIONS AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; REFIN = 1.25 V external. All specifications TMIN to TMAX, unless otherwise noted. Table 4.
PAGE 9
Data Sheet AD5390/AD5391/AD5392 AD5390-3 1 AD5392-31 AD5391-31 Unit Test Conditions/Comments 0.7 × DVDD 0.3 × DVDD ±1 0.05 × DVDD 50 0.7 × DVDD 0.3 × DVDD ±1 0.05 × DVDD 50 V min V max µA max V min ns max SMBus-compatible at DVDD < 3.6 V SMBus-compatible at DVDD < 3.6 V 0.4 DVDD − 0.5 DVDD − 0.1 ±1 5 0.4 DVDD − 0.5 DVDD − 0.1 ±1 5 V max V min V min µA max pF typ DVDD = 2.7 V to 5.5 V, sinking 200 µA DVDD = 2.7 V to 3.6 V, SDO only, sourcing 200 µA DVDD = 4.5 V to 5.
PAGE 10
AD5390/AD5391/AD5392 Data Sheet AD5390-3/AD5391-3/AD5392-3 AC CHARACTERISTICS AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V; CL = 200 pF to AGND. Table 5. Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time AD5390/AD5392 AD5391 Slew Rate 2 Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude Channel-to-Channel Isolation DAC-to-DAC Crosstalk Digital Crosstalk Digital Feedthrough OUTPUT NOISE (0.
PAGE 11
Data Sheet AD5390/AD5391/AD5392 TIMING CHARACTERISTICS SERIAL SPI-, QSPI-, MICROWIRE-, AND DSP-COMPATIBLE INTERFACE DVDD = 2 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. Table 6. 3-Wire Serial Interface 1 Parameter 2, 3 t1 t2 t3 t4 t5 4 t6 4 t7 t7 t8 t9 t104 t11 t124 t13 t14 t15 t16 t17 t17 t18 t19 t20 5 t214 t224 t234 Limit at TMIN, TMAX 33 13 13 13 13 33 10 50 5 4.
PAGE 12
AD5390/AD5391/AD5392 Data Sheet t1 SCLK 1 24 2 t3 t4 SYNC t7 t2 t5 t6 t8 t9 DB23 DIN 24 DB0 t10 BUSY t11 t12 t13 LDAC1 t17 t14 VOUT 1 t15 t13 LDAC2 t17 t16 VOUT 2 t18 CLR t19 1LDAC ACTIVE DURING BUSY 2LDAC ACTIVE DURING BUSY 03773-005 VOUT Figure 3. Serial Interface Timing Diagram (Standalone Mode) SCLK 24 48 t7A SYNC DB0 DB23' DB0 INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION SDO DB23 UNDEFINED DB0 SELECTED REGISTER DATA CLOCKED OUT Figure 4.
PAGE 13
Data Sheet AD5390/AD5391/AD5392 I2C SERIAL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. Table 7. I2C Serial Interface 1 Parameter 2 FSCL t1 t2 t3 t4 t5 t6 3 t7 t8 t9 t10 t11 CB 4 Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 300 0 300 20 + 0.
PAGE 14
AD5390/AD5391/AD5392 Data Sheet ABSOLUTE MAXIMUM RATINGS Transient currents of up to 100 mA do not cause SCR latch-up. TA = 25°C, unless otherwise noted. Table 8. Parameter AVDD to AGND DVDD to DGND Digital Inputs to DGND Digital Outputs to DGND VREF to AGND REFOUT to AGND AGND to DGND VOUTX to AGND ESD HBM FICSM Operating Temperature Range Commercial (B Version) Storage Temperature Range Junction Temperature (TJ max) 64-Lead LFCSP, θJA 52-Lead LQFP, θJA Reflow Soldering Peak Temperature Rating −0.
PAGE 15
Data Sheet AD5390/AD5391/AD5392 NC NC NC NC NC NC REF_GND REFOUT/REFIN SIGNAL_GND 1 DAC_GND 1 AVDD 1 VOUT 0 VOUT 1 VOUT 2 VOUT 3 VOUT 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLR DGND SYNC/AD0 DIN/SDA SCLK/SCL SDO DVDD DGND DGND DVDD DVDD DGND SPI/I2C PD DCEN/AD1 LDAC DGND SYNC/AD0 DIN/SDA SCLK/SCL SDO DVDD DGND DVDD DVDD DGND SPI/I2C PD DCEN/AD1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PIN CONFIGURATONS AND FUNCTION DESCRIPTIONS 52 51 50 49 48 47 46 45 44 43 42 41 40 PIN 1 INDICATOR AD5390/
PAGE 16
AD5390/AD5391/AD5392 Data Sheet Table 9. Pin Function Descriptions Mnemonic VOUT X SIGNAL_GND 1, SIGNAL_GND 2 DAC_GND 1, DAC_GND 2 AGND 1, AGND 2 AVDD 1, AVDD 2 DGND DVDD REF_GND REFOUT/REFIN MON_OUT MON_IN 1, MON_IN 2 SYNC/AD0 DCEN/AD1 SDO BUSY LDAC CLR RESET Function Buffered Analog Outputs for Channel X. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω.
PAGE 17
Data Sheet Mnemonic PD AD5390/AD5391/AD5392 TEST Function Power-Down (level-sensitive, active high). Used to place the device in low power mode, in which the device consumes 1 µA analog current and 20 µA digital current. In power-down mode, all internal analog circuitry is placed in low power mode; the analog output is configured as high impedance outputs or provides a 100 kΩ load to ground, depending on how the power-down mode is configured. The serial interface remains active during power-down.
PAGE 18
AD5390/AD5391/AD5392 Data Sheet TERMINOLOGY Relative Accuracy or Endpoint Linearity (INL) A measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error and is expressed in least significant bits (LSBs). Differential Nonlinearity (DNL) The difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
PAGE 19
Data Sheet AD5390/AD5391/AD5392 TYPICAL PERFORMANCE CHARACTERISTICS 1.00 2.0 AVDD = DVDD = 5.5V VREF = 2.5V TA = 25°C 1.5 0.75 0.50 0 –0.5 0.25 0 –0.25 –1.0 –0.50 –1.5 –0.75 –2.0 0 4096 8192 INPUT CODE 12288 16384 –1.00 03773-043 INL ERROR (LSB) 0.5 03773-040 0 1024 1536 2048 2560 3072 3584 4096 3584 4096 INPUT CODE Figure 14. Typical AD5391-5 INL Plot Figure 11. AD5390-5/AD5392-5 Typical INL Plot 1.00 2.0 AVDD = DVDD = 3V VREF = 1.25V TA = 25°C 1.5 0.75 1.0 0 –0.
PAGE 20
AD5390/AD5391/AD5392 Data Sheet 6 FULL SCALE 5 BUSY AVDD = DVDD = 5V VREF = 2.5V TA = 25°C 3/4 SCALE 4 MIDSCALE VOUT (V) 3 2 1/4 SCALE VOUT 1 ZERO SCALE –1 –40 –20 –10 –5 –2 0 2 CURRENT (mA) 5 10 20 03773-049 0 03773-100 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C 40 Figure 20. AD539x-5 Source and Sink Capability Figure 17. AD539x Exiting Soft Power-Down 0.20 AVDD = 5V VREF = 2.5V TA = 25°C 0.15 PD ERROR VOLTAGE (V) 0.10 VOUT 0 –0.05 (VDD–VOUT) AT FULL-SCALE SOURCING CURRENT –0.
PAGE 21
Data Sheet AD5390/AD5391/AD5392 1.260 DVDD = 5.5V VIH = DVDD VIL = DGND TA = 25°C 10 NUMBER OF UNITS 8 1.250 6 4 1.245 0 2 4 6 8 10 12 TIME (µs) 03773-104 0 1.240 0.5 Figure 23. AD539x-3 Glitch Impulse 0.6 0.7 0.8 DIDD (mA) 0.9 1.0 03773-107 2 Figure 26. AD539x DIDD Histogram 2.456 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C 14ns/SAMPLE NUMBER 2.455 LDAC AMPLITUDE (V) 2.454 VOUT 2.453 2.452 2.451 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C 2.
PAGE 22
AD5390/AD5391/AD5392 Data Sheet 6 AVDD = DVDD = 5V TA = 25°C DAC LOADED WITH MIDSCALE EXTERNAL REFERENCE Y AXIS = 5µV/DIV X AXIS = 100ms/DIV 5 AVDD = DVDD = 3V VREF = 1.25V TA = 25°C 4 VOUT (V) 3/4 SCALE 3 FULL SCALE MIDSCALE 2 1 ZERO SCALE –1 –40 –20 –10 –5 1/4 SCALE –2 0 2 CURRENT (mA) 5 10 20 40 Figure 30. AD539x-3 Source and Sink Current Capability Figure 29. 0.1 Hz to 10 Hz Output Noise Plot Rev.
PAGE 23
Data Sheet AD5390/AD5391/AD5392 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE The AD5390/AD5391 are complete single-supply, 16-channel, voltage output DACs offering a resolution of 14 bits and 12 bits, respectively. The AD5392 is a complete single-supply, 8-channel, voltage output DAC offering 14-bit resolution. All devices are available in a 64-lead LFCSP and 52-lead LQFP, and feature serial interfaces. This family includes an internal select-able 1.25 V/2.
PAGE 24
AD5390/AD5391/AD5392 Data Sheet DATA DECODING AD5391 AD5390/AD5392 The AD5391 contains an internal 12-bit data bus. The input data is decoded depending on the value loaded to the REG1 and REG0 bits of the input serial register. The input data from the serial input register is loaded into the addressed DAC input register, offset (c) register, or gain (m) register. The format data and the offset (c) and gain (m) register contents are shown in Table 14 to Table 16.
PAGE 25
Data Sheet AD5390/AD5391/AD5392 INTERFACES The AD5390/AD5391/AD5392 contain a serial interface that can be programmed to be DSP-, SPI-, and MICROWIREcompatible, or I2C-compatible. The SPI/I2C pin is used to select the interface mode. Logic 1 pin to configure this mode of operation. The serial interface control pins are described in Table 17. Table 17.
PAGE 26
AD5390/AD5391/AD5392 Data Sheet Standalone Mode The serial clock can be either a continuous or a gated clock. A continuous SCLK source can be used only if the SYNC can be held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and SYNC taken high after the final clock to latch the data. By connecting the daisy-chain enable (DCEN) pin low, standalone mode is enabled.
PAGE 27
Data Sheet AD5390/AD5391/AD5392 I2C SERIAL INTERFACE Repeated START Condition The AD5390/AD5391/AD5392 feature an I2C-compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the DACs and the master at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing diagram. A repeated START (Sr) condition may indicate a change of data direction on the bus.
PAGE 28
AD5390/AD5391/AD5392 Data Sheet I2C WRITE OPERATION DAC to be addressed and is also acknowledged by the DAC. Address Bits A3 to A0 address all channels on the AD5390/ AD5391. Address Bits A2 to A0 address all channels on the AD5392. Address Bit A3 is a zero on the AD5392. Two bytes of data are then written to the DAC, as shown in Figure 33. A STOP condition follows. This lets the user update a single channel within the AD539x at any time and requires four bytes of data to be transferred from the master.
PAGE 29
Data Sheet AD5390/AD5391/AD5392 3-BYTE MODE on the AD5392. Address Bit A3 is a zero on the AD5392. This is then followed by the two data bytes. REG1 and REG0 determine the register to be updated. The 3-byte mode lets the user update more than one channel in a write sequence without having to write the device address byte each time. The device address byte is required only once and subsequent channel updates require the pointer byte and the data bytes.
PAGE 30
AD5390/AD5391/AD5392 Data Sheet 2-BYTE MODE The REG0 and REG1 bits in the data byte determine the register to be updated. In this mode, following the initialization, only the two data bytes are required to update a channel. The channel address automatically increments from Address 0 to the final address and then returns to the normal 3-byte mode of operation. This mode allows transmission of data to all channels in one block and reduces the software overhead in configuring all channels.
PAGE 31
Data Sheet AD5390/AD5391/AD5392 AD539x ON-CHIP SPECIAL FUNCTION REGISTERS The AD539x family of parts contains a number of special function registers (SFRs) as shown in Table 22. SFRs are addressed with REG1 = 0 and REG0 = 0 and are decoded using Address Bit A3 to Bit A0. Table 22.
PAGE 32
AD5390/AD5391/AD5392 Data Sheet Table 23.
PAGE 33
Data Sheet AD5390/AD5391/AD5392 CONTROL REGISTER WRITE Table 25 shows the control register contents for the AD5390 and the AD5392. Table 26 provides bit descriptions. Note that REG1 = REG0 = 0, A3 to A0 = 1100, and DB13 to DB0 contain the control register data. Table 25. AD5390/AD5392 Control Register Contents MSB CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 LSB CR0 Table 26.
PAGE 34
AD5390/AD5391/AD5392 Data Sheet Table 27 shows the control register contents of the AD5391. Table 28 provides bit descriptions. Note that REG1 = REG0 = 0, A3 to A0 = 1100, and DB13 to DB0 contain the control register data. Table 27. AD5391 Control Register Contents MSB CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 LSB CR0 Table 28. AD5391 Bit Descriptions Bit CR11 CR10 CR9 CR8 CR7 CR6 CR5 to CR2 CR1 to CR0 Description Power-Down Status.
PAGE 35
Data Sheet AD5390/AD5391/AD5392 HARDWARE FUNCTIONS RESET FUNCTION POWER-ON RESET Bringing the RESET line low resets the contents of all internal registers to their power-on reset state. RESET is a negative edgesensitive input. The default corresponds to m at full scale and c at zero scale. The contents of all DAC registers are cleared by setting the outputs to 0 V. This sequence takes 270 µs maximum. The falling edge of RESET initiates the reset process.
PAGE 36
AD5390/AD5391/AD5392 Data Sheet DVDD AD539x to PIC16C6x/7x AD539x The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON)—see the PIC16/17 Microcontroller User Manual. In Figure 38, I/O port RA1 is used to pulse SYNC and enable the serial port of the AD539x.
PAGE 37
Data Sheet AD5390/AD5391/AD5392 APPLICATION INFORMATION In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD539x is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board.
PAGE 38
AD5390/AD5391/AD5392 Data Sheet AD539x MONITOR FUNCTION The AD5390 contains a channel monitor function consisting of a multiplexer addressed via the interface, allowing any channel output to be routed to this pin for monitoring using an external ADC. The channel monitor function must be enabled in the control register before any channels are routed to the MON_OUT pin. Table 23 and Table 24 contain the decoding information required to route any channel on the AD5390, AD5391, and AD5392 to the MON_OUT pin.
PAGE 39
Data Sheet AD5390/AD5391/AD5392 Power Amplifier Control 0.1µF PHASE SHIFT 2.5V REFERENCE 4R 2R ±10V RANGE R VOUT 3 R 1/4 OP747/ 1/4 OP4177 4R ±5V RANGE R VOUT 0 R AD539x-5 2R 1/4 OP747/ 1/4 OP4177 0V TO 5V RANGE VOUT 1 0V TO 10V RANGE VOUT 4 1/4 OP747/ 1/4 OP4177 R I SINK VOUT 2 R 1/4 OP747/ 1/4 OP4177 IBIAS R1 03773-033 Multistage power amplifier designs require a large number of setpoints in the operation and control of the output stage.
PAGE 40
AD5390/AD5391/AD5392 Data Sheet OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.60 MAX 0.60 MAX 64 49 1 PIN 1 INDICATOR 48 PIN 1 INDICATOR 8.85 8.75 SQ 8.65 0.50 BSC 0.50 0.40 0.30 33 32 17 7.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 SEATING PLANE FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF 06-13-2012-C 12° MAX 16 0.
PAGE 41
Data Sheet AD5390/AD5391/AD5392 ORDERING GUIDE Model 1 AD5390BCPZ-3 Temperature Range −40°C to +85°C Resolution 14-bit AVDD 2.7 V to 3.6 V Output Channels 16 Linearity Error (LSBs) ±4 Package Description 64-Lead LFCSP_VQ Package Option CP-64-3 AD5390BCPZ-3-REEL AD5390BCPZ-3-REEL7 AD5390BCPZ-5 −40°C to +85°C −40°C to +85°C −40°C to +85°C 14-bit 14-bit 14-bit 2.7 V to 3.6 V 2.7 V to 3.6 V 4.5 V to 5.
PAGE 42
AD5390/AD5391/AD5392 Data Sheet NOTES Rev.
PAGE 43
Data Sheet AD5390/AD5391/AD5392 NOTES Rev.
PAGE 44
AD5390/AD5391/AD5392 Data Sheet NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03773-0-6/12(E) Rev.