Datasheet

Data Sheet AD5383
Rev. C | Page 7 of 40
Parameter AD5383-3
1
Unit Test Conditions/Comments
Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns
LOGIC OUTPUTS (BUSY, SDO)
3
V
OL
, Output Low Voltage 0.4 V max Sinking 200 µA
V
OH
, Output High Voltage DV
DD
– 0.5 V min Sourcing 200 µA
High Impedance Leakage Current ±1 µA max SDO only
High Impedance Output Capacitance 5 pF typ SDO only
LOGIC OUTPUT (SDA)
3
V
OL
, Output Low Voltage 0.4 V max I
SINK
= 3 mA
0.6 V max I
SINK
= 6 mA
Three-State Leakage Current ±1 µA max
Three-State Output Capacitance 8 pF typ
POWER REQUIREMENTS
AV
DD
2.7/3.6 V min/max
DV
DD
2.7/5.5 V min/max
Power Supply Sensitivity
3
ΔMidscale/ΔΑV
DD
–85 dB typ
AI
DD
0.375 mA/channel max Outputs unloaded, boost off; 0.25 mA/channel typ
0.475 mA/channel max Outputs unloaded, boost on; 0.325 mA/channel typ
DI
DD
1
mA max
V
IH
= DV
DD
, V
IL
= DGND.
AI
DD
(Power-Down) 20 µA max Typically 200 nA
DI
DD
(Power-Down) 20 µA max Typically 1 µA
Power Dissipation 39 mW max Outputs unloaded, boost off; AV
DD
= DV
DD
= 3 V
1
AD5383-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C.
2
Accuracy guaranteed from V
OUT
= 10 mV to AVDD – 50 mV.
3
Guaranteed by characterization, not production tested.
4
Default on the AD5383-3 is 1.25 V. Programmable to 2.5 V via CR10 in the AD5383 control register; operating the AD5383-3 with a 2.5 V reference leads to degraded
accuracy specifications and limited input code range.
AC CHARACTERISTICS
1
AV
DD
= 4.5 V to 5.5 V or 2.7 V to 3.6 V; DV
DD
= 2.7 V to 5.5 V; AGND = DGND = 0 V.
Table 4.
Parameter All Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
2
¼ scale to ¾ scale change settling to ±1 LSB
3 µs typ Boost mode off, CR9 = 0
8 µs max Boost mode off, CR9 = 0
Slew Rate
2
1.5 V/µs typ Boost mode off, CR9 = 0
2.5 V/µs typ Boost mode on, CR9 = 1
Digital-to-Analog Glitch Energy 12 nV-s typ
Glitch Impulse Peak Amplitude 15 mV typ
DAC-to-DAC Crosstalk 1 nV-s typ See Terminology section
Digital Crosstalk 0.8 nV-s typ
Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test
Output Noise 0.1 Hz to 10 Hz 15 µV p-p typ External reference, midscale loaded to DAC
40 µV p-p typ Internal reference, midscale loaded to DAC
Output Noise Spectral Density
@ 1 kHz 150 nV/√Hz typ
@ 10 kHz
100
nV/√Hz typ
1
Guaranteed by design and characterization, not production tested.
2
The slew rate can be programmed via the current boost control bit (CR9) in the AD5383 control register.