32-Channel, 3 V/5 V, Single-Supply, 12-Bit, denseDAC® AD5383 Data Sheet FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic INL error: ±1 LSB max On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier Power-down mode Package type: 100-lead LQFP (14 mm × 14 mm) User Interfaces Parallel Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible, featuring data readback) I2C-compatible Robust 6.
AD5383 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SFR Commands .......................................................................... 22 Integrated Functions ........................................................................ 1 Hardware Functions ....................................................................... 25 Applications ......................................................................
Data Sheet AD5383 GENERAL DESCRIPTION The AD5383 is a complete, single-supply, 32-channel, 12-bit denseDAC® available in a 100-lead LQFP package. All 32 channels have an on-chip output amplifier with rail-to-rail operation. The AD5383 includes a programmable internal 1.25 V/2.
AD5383 Data Sheet SPECIFICATIONS AD5383-5 SPECIFICATIONS AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Data Sheet Parameter LOGIC INPUTS (SDA, SCL ONLY) VIH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance Glitch Rejection LOGIC OUTPUTS (BUSY, SDO)3 VOL, Output Low Voltage VOH, Output High Voltage VOL, Output Low Voltage VOH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)3 VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD DVDD Po
AD5383 Data Sheet AD5383-3 SPECIFICATIONS AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
Data Sheet Parameter Glitch Rejection LOGIC OUTPUTS (BUSY, SDO)3 VOL, Output Low Voltage VOH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)3 VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD DVDD Power Supply Sensitivity3 ΔMidscale/ΔΑVDD AIDD DIDD AIDD (Power-Down) DIDD (Power-Down) Power Dissipation AD5383 AD5383-3 1 50 Unit ns max Test Conditions/Comments Input filtering suppresses noise s
AD5383 Data Sheet TIMING CHARACTERISTICS SERIAL INTERFACE TIMING DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter 1, 2, 3 t1 t2 t3 t4 t5 4 t6 4 t7 t7A t8 t9 t104 t11 t124 t13 t14 t15 t16 t17 t18 t19 t20 5 t215 t225 t23 Limit at TMIN, TMAX 33 13 13 13 13 33 10 50 5 4.
Data Sheet AD5383 t1 24 SCLK t3 t4 t2 24 t5 t6 SYNC t7 t8 t9 DB0 DIN DB23 t10 t11 BUSY t13 t12 t17 LDAC1 t14 VOUT1 t15 t13 LDAC2 t17 t16 VOUT2 t18 CLR 03734-003 VOUT t19 1LDAC ACTIVE DURING BUSY 2LDAC ACTIVE AFTER BUSY Figure 3. Serial Interface Timing Diagram (Standalone Mode) SCLK 24 48 t7A SYNC DB23 DIN DB0 DB23 DB0 INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION UNDEFINED DB0 03734-004 DB23 SDO SELECTED REGISTER DATA CLOCKED OUT Figure 4.
AD5383 Data Sheet I2C SERIAL INTERFACE TIMING DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 6. Parameter 1, 2 FSCL t1 t2 t3 t4 t5 t6 3 t7 t8 t9 t10 t11 Cb Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 300 0 300 20 + 0.
Data Sheet AD5383 PARALLEL INTERFACE TIMING DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 7. Parameter 1, 2, 3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 4 t104 t114, 5 t12 t13 t14 t15 t16 t17 t18 t19 t20 Limit at TMIN, TMAX 4.5 4.5 20 20 0 0 4.5 4.
AD5383 Data Sheet t0 t1 REG0, REG1, A4..A0 t4 CS t5 t2 t9 WR t3 t8 t15 t7 t6 DB11..DB0 t10 t11 BUSY t13 t12 t18 LDAC1 t14 VOUT1 t16 LDAC2 t13 t18 t17 VOUT2 CLR t19 1LDAC ACTIVE DURING BUSY 2LDAC ACTIVE AFTER BUSY Figure 7. Parallel Interface Timing Diagram Rev.
Data Sheet AD5383 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted 1. Table 8. Parameter AVDD to AGND DVDD to DGND Digital Inputs to DGND SDA/SCL to DGND Digital Outputs to DGND REFIN/REFOUT to AGND AGND to DGND VOUTx to AGND Analog Inputs to AGND MON_IN Inputs to AGND MON_OUT to AGND ESD HBM FICDM Operating Temperature Range Commercial (B Version) Storage Temperature Range JunctionTemperature (TJ Max) 100-Lead LQFP Package θJA Thermal Impedance Reflow Soldering Peak Temperature 1 Rating –0.
AD5383 Data Sheet 76 75 PIN 1 IDENTIFIER 2 3 4 74 73 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 13 14 AD5383 64 TOP VIEW (Not to Scale) 63 62 15 61 16 60 17 59 18 58 19 57 20 56 21 22 55 23 24 53 52 25 51 50 49 48 47 46 45 44 43 42 41 40 38 39 37 36 35 34 33 32 31 30 29 28 NC NC NC NC VOUT5 VOUT6 VOUT7 NC NC MON_IN1 MON_IN2 MON_IN3 MON_IN4 NC MON_OUT VOUT8 VOUT9 VOUT10 VOUT11 VOUT12 DAC_GND2 SIGNAL_GND2 VOUT13 VOUT14 VOUT15 27 54 RESET DB5 D
Data Sheet Mnemonic MON_INx SER/PAR CS/(SYNC/AD0) WR/(DCEN/AD1) DB11 to DB0 A4 to A0 REG1, REG0 SDO/(A/B) BUSY LDAC CLR RESET AD5383 Function MON_IN Monitor Input Pins. The AD5383 contains four monitor input pins that allow the user to connect input signals within the maximum ratings of the device to these pins for monitoring purposes. Any of the signals applied to the MON_IN pins along with the 32 output channels can be switched to the MON_OUT pin via software.
AD5383 Mnemonic PD FIFO EN DB9/(SPI/I2C) DB10/(SCLK/SCL) DB11/(DIN/SDA) NC Data Sheet Function Power Down (Level Sensitive, Active High). PD is used to place the device in low power mode where the device consumes 2 µA analog supply current and 20 µA digital supply current.
Data Sheet AD5383 TERMINOLOGY Relative Accuracy Relative accuracy, or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error, and is expressed in LSB. Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes.
AD5383 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.00 1.00 AVDD = 5V REFIN = 2.5V TA = 25°C 0.75 0.50 0.25 0 –0.25 0.25 0 –0.25 –0.50 –0.50 –0.75 –0.75 –1.00 0 512 1024 1536 2048 2560 INPUT CODE 3072 3584 4096 –1.00 0 512 Figure 9. Typical AD5383-5 INL Plot 1024 1536 2048 2560 INPUT CODE 3072 3584 4096 03734-012 INL ERROR (LSB) 0.50 03734-009 INL ERROR (LSB) AVDD = 3V REFIN = 1.25V TA = 25°C 0.75 Figure 12. Typical AD5383-3 INL Plot 2.510 1.
Data Sheet AD5383 AVDD = 5.5V VREF = 2.5V TA = 25°C 14 PERCENTAGE OF UNITS (%) 12 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C 10 VDD 8 6 VOUT 4 9 10 AIDD (mA) 11 CH1 2.00V Figure 15. AIDD Histogram CH2 20.0mV M100µs CH1 2.08V 03734-018 8 03734-015 2 Figure 18. Power-Up Transient 40 DVDD = 5.5V VIH = DVDD VIL = DGND TA = 25°C 10 35 30 FREQUENCY 6 4 25 20 15 10 2 5 0.7 0.8 DIDD (mA) 0.9 1.0 0 0 1.0 2.0 3.0 4.0 5.0 –5.0 –4.0 –3.0 –2.0 –1.0 –4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.
AD5383 Data Sheet 6 6 AVDD = DVDD = 3V VREF = 1.25V TA = 25°C FULL-SCALE 5 5 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C 3/4 SCALE 4 4 3 2 VOUT (V) VOUT (V) 3/4 SCALE MIDSCALE 1/4 SCALE 3 FULL-SCALE MIDSCALE 2 1 1 ZERO-SCALE 0 ZERO-SCALE –20 –10 –5 –2 0 2 CURRENT (mA) 5 10 20 40 –1 –40 03734-021 –1 –40 Figure 21. AD5383-5 Output Amplifier Source and Sink Capability 0.20 5 10 20 40 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C 14ns/SAMPLE NUMBER 2.454 ERROR AT ZERO SINKING CURRENT 0.
Data Sheet AD5383 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The AD5383 is a complete, single-supply, 32-channel voltage output DAC that offers 12-bit resolution. The part is available in a 100-lead LQFP package and features both a parallel and a serial interface. This product includes an internal, software selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used to drive the buffered reference inputs; alternatively, an external reference can be used to drive these inputs.
AD5383 Data Sheet ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) Soft CLR The AD5383 contains a number of special function registers (SFRs), as outlined in Table 14. SFRs are addressed with REG1 = REG0 = 0 and are decoded using Address Bit A4 to Address Bit A0. REG1 = REG0 = 0, A4 to A0 = 00010 DB11 to DB0 = don’t care Table 14.
Data Sheet AD5383 Table 15. Control Register Contents MSB CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 LSB CR0 Control Register Write/Read REG1 = REG0 = 0, A4 to A0 = 01100, R/W status determines if the operation is a write (R/W = 0) or a read (R/W = 1). DB11 to DB0 contains the control register data. Control Register Contents CR11: Power-Down Status. This bit is used to configure the output amplifier state in power down. CR11 = 1. Amplifier output is high impedance (default on power-up).
AD5383 Data Sheet Table 17.
Data Sheet AD5383 HARDWARE FUNCTIONS RESET FUNCTION FIFO OPERATION IN PARALLEL MODE Bringing the RESET line low resets the contents of all internal registers to their power-on reset state. RESET is a negative edgesensitive input. The default corresponds to m at full scale and to c at zero scale. The contents of the DAC registers are cleared, setting VOUT0 to VOUT31 to 0 V. This sequence takes 270 µs max.
AD5383 Data Sheet INTERFACES Figure 3 and Figure 5 show timing diagrams for a serial write to the AD5383 in standalone and daisy-chain modes. The 24-bit data-word format for the serial interface is shown in Table 18. The AD5383 contains both parallel and serial interfaces. Furthermore, the serial interface can be programmed to be SPI-, DSP-, MICROWIRE-, or I2C-compatible. The SER/PAR pin selects parallel and serial interface modes.
Data Sheet AD5383 Daisy-Chain Mode Readback Mode For systems that contain several devices, the SDO pin may be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. With R/W = 1, Bits A4 to A0, in association with Bits REG1 and REG0, select the register to be read.
AD5383 Data Sheet I2C SERIAL INTERFACE The AD5383 features an I2C-compatible, 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the AD5383 and the master at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing diagram that incorporates three different modes of operation.
Data Sheet AD5383 SCL 1 SDA 0 1 0 1 AD1 AD0 START COND BY MASTER R/W 0 ACK BY AD538x MSB 0 0 A4 A3 A2 A1 A0 ACK BY AD538x ADDRESS BYTE POINTER BYTE SCL REG1 REG0 MSB LSB MSB LSB ACK BY AD538x ACK BY AD538x MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE STOP COND BY MASTER 03734-031 SDA Figure 31.
AD5383 Data Sheet 2-Byte Mode PARALLEL INTERFACE Following initialization of 2-byte mode, the user can sequentially update channels. The device address byte is only required once, and the address pointer is configured for autoincrement or burst mode. The SER/PAR pin must be tied low to enable the parallel interface and disable the serial interfaces. Figure 7 shows the timing diagram for a parallel write.
Data Sheet AD5383 MICROPROCESSOR INTERFACING Parallel Interface The AD5383 can be interfaced to a variety of 16-bit microcontrollers or DSP processors. Figure 35 shows the AD5383 family interfaced to a generic 16-bit microcontroller/DSP processor. The lower address lines from the processor are connected to A0 to A4 on the AD5383. The upper address lines are decoded to provide a CS, LDAC signal for the AD5383.
AD5383 Data Sheet AD5383 to PIC16C6x/7x AD5383 SER/PAR SDO SDO/RC5 DIN SCK/RC3 SCLK RA1 SYNC SPI/I2C 03734-036 RESET SDI/RC4 Figure 36. AD5383-to-PIC16C6x/7x Interface RESET RxD SDO DIN TxD SCLK P1.1 SYNC SPI/I2C Figure 37. AD5383-to-8051 Interface AD5383 to ADSP-2101/ADSP-2103 Figure 38 shows a serial interface between the AD5383 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in SPORT transmit alternate framing mode.
Data Sheet AD5383 APPLICATION INFORMATION In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5383 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board.
AD5383 Data Sheet CHANNEL MONITOR FUNCTION The AD5383 contains a channel monitor function that consists of a multiplexer addressed via the interface, allowing any channel output to be routed to this pin for monitoring using an external ADC. The channel monitor function must be enabled in the control register before any channels are routed to MON_OUT. Table 17 contains the decoding information needed to route any channel to MON_OUT. To three-state MON_OUT, select Channel Address 63.
Data Sheet AD5383 DATA REGISTER A DAC REGISTER 12-BIT DAC VOUT LDAC CONTROL INPUT A/B 03734-042 DATA REGISTER B INPUT INPUT DATA REGISTER Figure 42. Toggle Mode Function ADD PORTS DROP PORTS OPTICAL SWITCH PHOTODIODES 11 ATTENUATOR 12 DWDM IN DWDM OUT ATTENUATOR FIBRE AWG AWG FIBRE 1n–1 ATTENUATOR 1n ATTENUATOR TIA/LOG AMP (AD8304/AD8305) N:1 MULTIPLEXER CONTROLLER 16-BIT ADC ADG731 (32:1 MUX) AD7671 (0-5V, 1MSPS) 03734-043 AD5383, 32-CHANNEL, 12-BIT DAC Figure 43.
AD5383 Data Sheet UTILIZING THE FIFO systems, as many as 320 channels need to be updated within 25 µs to 30 µs. 320 channels require the use of 10 AD5383s. With FIFO mode enabled, the data write cycle time is 40 ns; therefore, each group consisting of 32 channels can be fully loaded in 1.28 µs. In FIFO mode, a complete group of 32 channels updates in 11.5 µs. The time taken to update all 320 channels is 11.5 µs + 9 × 1.28 µs = 23 µs. Figure 44 shows the FIFO operation scheme.
Data Sheet AD5383 OUTLINE DIMENSIONS 16.20 16.00 SQ 15.80 1.60 MAX 0.75 0.60 0.45 100 1 76 75 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY 51 50 25 26 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW 0.27 0.22 0.17 051706-A 1.45 1.40 1.35 COMPLIANT TO JEDEC STANDARDS MS-026-BED Figure 45.
AD5383 Data Sheet NOTES Rev.
Data Sheet AD5383 NOTES Rev.
AD5383 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03734-0-10/12(C) Rev.
