Datasheet
AD5382 Data Sheet
Rev. C | Page 32 of 40
AD5382 to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured as
an SPI master with the Clock Polarity bit = 0. This is done by
writing to the synchronous serial port control register (SSPCON).
See the PIC16/17 Microcontroller User Manual. In this example
I/O, Port RA1 is being used to pulse
SYNC
and enable the serial
port of the AD5382. This microcontroller transfers only eight
bits of data during each serial transfer operation; therefore, three
consecutive read/write operations may be needed depending on
the mode. Figure 35 shows the connection diagram.
03733-036
PIC16C6X/7X
1
AD5382
1
SDI/RC4
SDO/RC5
SCK/RC3
RA1
SDO
RESET
SER/PAR
DIN
SCLK
SYNC
SPI/I
2
C
DVDD
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 35. AD5382-to-PIC16C6x/7x Interface
AD5382 to 8051
The AD5382 requires a clock synchronized to the serial data.
The 8051 serial interface must therefore be operated in Mode 0.
In this mode, serial data enters and exits through RxD, and a
shift clock is output on TxD. Figure 36 shows how the 8051 is
connected to the AD5382. Because the AD5382 shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD5382
requires its data to be MSB first. Since the 8051 outputs the
LSB first, the transmit routine must take this into account.
03733-037
8XC51
1
AD5382
1
RxD
TxD
P1.1
SDO
RESET
SER/PAR
DIN
SCLK
SYNC
SPI/I
2
C
DVDD
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 36. AD5382-to-8051 Interface
AD5382 to ADSP-2101/ADSP-2103
Figure 37 shows a serial interface between the AD5382 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in SPORT transmit alternate framing mode.
The ADSP-2101/ADSP-2103 SPORT is programmed through
the SPORT control register and should be configured as follows:
internal clock operation, active low framing, and 16-bit word
length. Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled.
03733-038
ADSP-2101/
ADSP-2103
1
AD5382
1
DR
DT
SCK
TFS
RFS
SDO
RESET
SER/PAR
DIN
SCLK
DVDD
SPI/I
2
C
SYNC
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 37. AD5382-to-ADSP-2101/ADSP-2103 Interface