Datasheet

32-Channel, 3 V/5 V, Single-Supply,
14-Bit
dense
DAC
Data Sheet
AD5382
Rev. C
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infringements of patents or other rights of third parties that may result from its use.
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81.329.4700 www.analog.com
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FEATURES
Guaranteed monotonic
INL error: ±4 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: 40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package type: 100-lead LQFP (14 mm × 14 mm)
User interfaces:
Parallel
Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,
featuring data readback)
I
2
C-compatible
Robust 6.5 kV HBM and 2 kV FICDM ESD rating
INTEGRATED FUNCTIONS
Channel monitor
Simultaneous output update via
LDAC
Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User-programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor
APPLICATIONS
Variable optical attenuators (VOAs)
Level setting (ATE)
Optical micro-electro-mechanical systems (MEMS)
Control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
VOUT0
DAC 0
DAC
REG0
INPUT
REG0
1414
1414
14
14
m REG0
c REG0
1.25V/2.5V
REFERENCE
POWER-ON
RESET
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
DAC 1
DAC
REG1
INPUT
REG1
1414 1414
14
14
m REG1
c REG1
VOUT6
DAC 6
DAC
REG6
INPUT
REG6
1414 1414
14
14
m REG6
c REG6
VOUT7
VOUT8
DAC 7
DAC
REG7
INPUT
REG7
1414 1414
14
14
m REG7
c REG7
×4
03733-001
FIFO
+
STATE
MACHINE
+
CONTROL
LOGIC
INTERFACE
CONTROL
LOGIC
DB13/(DIN/SDA)
DB12/(SCLK/SCL)
DB11/(SPI/I
2
C)
DB10
A4
A0
REG0
REG1
RESET
BUSY
CLR
MON_IN1
MON_IN2
MON_IN3
MON_IN4
PD
SER/PAR
FIFO EN
CS/(SYNC/AD0)
WR/(DCEN/AD1)
SDO
36-TO-1
MUX
VOUT0………VOUT31
MON_OUT LDAC
VOUT31
DVDD (×3) DGND (×3) AVDD (×4) AGND (×4) DAC_GND (×4) REFGND REFOUT/REFIN SIGNAL_GND (×4)
AD5382
DB0
R
R
R
R
R
R
R
R
Figure 1.

Summary of content (40 pages)