32-Channel, 3 V/5 V, Single-Supply, 14-Bit denseDAC AD5382 Data Sheet FEATURES INTEGRATED FUNCTIONS Guaranteed monotonic INL error: ±4 LSB max On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier Power-down mode Package type: 100-lead LQFP (14 mm × 14 mm) User interfaces: Parallel Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible, featuring data readback) I2C-compatible Robust 6.
AD5382 Data Sheet TABLE OF CONTENTS General Description ......................................................................... 3 Asynchronous Clear Function.................................................. 25 Specifications..................................................................................... 4 BUSY and LDAC Functions...................................................... 25 AD5382-5 Specifications .............................................................
Data Sheet AD5382 GENERAL DESCRIPTION The AD5382 is a complete, single-supply, 32-channel, 14-bit denseDAC® available in a 100-lead LQFP package. All 32 channels have an on-chip output amplifier with rail-to-rail operation. The AD5382 includes an internal software-selectable 1.25 V/2.
AD5382 Data Sheet SPECIFICATIONS AD5382-5 SPECIFICATIONS AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; External REFIN = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2.
Data Sheet Parameter LOGIC INPUTS (SDA, SCL ONLY)3 VIH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance Glitch Rejection LOGIC OUTPUTS (BUSY, SDO)3 VOL, Output Low Voltage VOH, Output High Voltage VOL, Output Low Voltage VOH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)3 VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD DVDD P
AD5382 Data Sheet AD5382-3 SPECIFICATIONS AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3.
Data Sheet Parameter LOGIC OUTPUTS (BUSY, SDO)3 VOL, Output Low Voltage VOH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance LOGIC OUTPUT (SDA)3 VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS AVDD DVDD Power Supply Sensitivity3 ∆Midscale/∆ΑVDD AIDD DIDD AIDD (Power-Down) DIDD (Power-Down) Power Dissipation AD5382 AD5382-3 1 Unit Test Conditions/Comments 0.4 DVDD – 0.
AD5382 Data Sheet TIMING CHARACTERISTICS SPI-, QSPI-, MICROWIRE-, OR DSP-COMPATIBLE SERIAL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 5. Parameter 1, 2, 3 t1 t2 t3 t4 t5 4 t6 4 t7 t7A t8 t9 t104 t11 t12 4 t13 t14 t15 t16 t17 t18 t19 t20 5 t215 t225 t23 Limit at TMIN, TMAX 33 13 13 13 13 33 10 50 5 4.
Data Sheet AD5382 t1 24 SCLK t3 t4 t2 24 t5 t6 SYNC t7 t8 t9 DB0 DIN DB23 t10 BUSY t11 t13 t12 t17 LDAC1 t14 VOUT1 t15 t13 LDAC2 t17 t16 VOUT2 t18 CLR t19 03733-003 VOUT 1LDAC ACTIVE DURING BUSY 2LDAC ACTIVE AFTER BUSY Figure 3. Serial Interface Timing Diagram (Standalone Mode) SCLK 24 48 t7A SYNC DB0 DB23 DIN DB23 DB0 NOP CONDITION INPUT WORD SPECIFIES REGISTER TO BE READ DB0 03733-004 DB23 SDO SELECTED REGISTER DATA CLOCKED OUT UNDEFINED Figure 4.
AD5382 Data Sheet I2C SERIAL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 6. Parameter 1, 2 FSCL t1 t2 t3 t4 t5 t6 3 t7 t8 t9 t10 t11 Cb Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 300 0 300 20 + 0.
Data Sheet AD5382 PARALLEL INTERFACE DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications Tmin to Tmax, unless otherwise noted. Table 7. Parameter 1, 2, 3 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 4 t104 t114, 5 t12 t13 t14 t15 t16 t17 t18 t19 t20 Limit at TMIN, TMAX 4.5 4.5 20 20 0 0 4.5 4.
AD5382 Data Sheet t1 t0 REG0, REG1, A4...A0 t5 t4 CS t2 t9 WR t8 t3 t6 t15 t7 DB13...DB0 t10 t11 BUSY t12 t13 t18 LDAC1 t14 VOUT1 t16 LDAC2 t13 t18 t17 VOUT2 CLR t19 1LDAC ACTIVE DURING BUSY 2LDAC ACTIVE AFTER BUSY Figure 7. Parallel Interface Timing Diagram Rev.
Data Sheet AD5382 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted 1. Table 8. Parameter AVDD to AGND DVDD to DGND Digital Inputs to DGND SDA/SCL to DGND Digital Outputs to DGND REFIN/REFOUT to AGND AGND to DGND VOUTx to AGND Analog Inputs to AGND MON_IN Inputs to AGND MON_OUT to AGND Operating Temperature Range Commercial (B Version) Storage Temperature Range JunctionTemperature (TJ max) 100-lead LQFP Package θJAThermal Impedance Reflow Soldering Peak Temperature ESD HBM FICDM 1 Rating –0.
AD5382 Data Sheet 76 78 77 81 79 80 82 83 85 84 87 86 89 88 91 90 92 93 95 96 94 98 97 1 75 RESET 74 DB7 PIN 1 IDENTIFIER 2 3 4 73 DB6 72 DB5 5 71 DB4 6 70 DB3 69 DB2 7 8 68 DB1 67 DB0 9 10 66 REG0 65 REG1 11 12 13 14 AD5382 64 VOUT23 TOP VIEW (Not to Scale) 63 VOUT22 62 VOUT21 15 61 VOUT20 60 AVDD3 16 17 59 AGND3 18 58 DAC_GND3 57 SIGNAL_GND3 19 20 56 VOUT19 55 VOUT18 21 22 54 VOUT17 23 03733-008 50 49 48 47 46 45 44 43 42 41 40 38 39 37 3
Data Sheet Mnemonic MON_OUT MON_INx SER/PAR CS/(SYNC/AD0) WR/(DCEN/AD1) DB13–DB0 A4–A0 REG1, REG0 SDO/(A/B) BUSY LDAC CLR RESET AD5382 Function Monitor Output. When the monitor function is enabled, this pin acts as the output of a 36-to-1 channel multiplexer that can be programmed to multiplex one of Channels 0 to 31 or any of the monitor input pins (MON_IN1 to MON_IN4) to the MON_OUT pin.
AD5382 Data Sheet Mnemonic PD Function Power Down (Level Sensitive, Active High). PD is used to place the device in to low power mode where the device consumes 2 µA AIDD and 20 µA DIDD. In power-down mode, all internal analog circuitry is placed in low power mode, and the analog output is configured as a high impedance output or provides a 100 kΩ load to ground, depending on how the power-down mode is configured. The serial interface remains active during power-down.
Data Sheet AD5382 TERMINOLOGY Relative Accuracy DC Output Impedance Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error, and is expressed in LSB. This is the effective output source resistance. It is dominated by package lead resistance.
AD5382 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.0 2.0 AVDD = DVDD = 5.5V VREF = 2.5V TA = 25°C 1.5 1.0 0.5 0 –0.5 0.5 0 –0.5 –1.0 –1.0 –1.5 –1.5 0 4096 8192 INPUT CODE 12288 16384 –2.0 03733-009 –2.0 0 4096 Figure 9. Typical AD5382-5 INL Plot 8192 INPUT CODE 16384 12288 03733-012 INL ERROR (LSB) 1.0 INL ERROR (LSB) AVDD = DVDD = 3V VREF = 1.25V TA = 25°C 1.5 Figure 12. Typical AD5382-3 INL Plot 2.510 2.500 AVDD = DVDD = 5V VREF = 2.
Data Sheet AD5382 14 DVDD = 5.5V VIH = DVDD VIL = DGND TA = 25°C 10 12 10 NUMBER OF UNITS 8 6 4 8 6 4 2 2 0.6 0.7 0.8 DIDD (mA) 0.9 1.0 0 1 –1 0 INL ERROR DISTRIBUTION (LSB) –2 Figure 15. DIDD Histogram 03733-019 0.5 03733-107 0 2 Figure 18. INL Error Distribution AVDD = DVDD = 5V VREF = 2.5V TA = 25°C BUSY VDD VOUT 03733-102 03733-017 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C VOUT Figure 16. Exiting Soft Power-Down Figure 19.
AD5382 Data Sheet 0.20 2.456 AVDD = 5V VREF = 2.5V TA = 25°C 0.15 AVDD = DVDD = 5V VREF = 2.5V TA = 25°C 14ns/SAMPLE NUMBER 2.455 2.454 ERROR AT ZERO SINKING CURRENT 0.05 AMPLITUDE (V) 0 –0.05 2.452 2.451 (VDD–VOUT) AT FULL-SCALE SOURCING CURRENT –0.10 2.453 0 0.25 0.50 0.75 1.00 1.25 ISOURCE/ISINK (mA) 1.50 1.75 2.00 03733-022 –0.20 2.449 0 AVDD = 5V TA = 25°C REFOUT DECOUPLED WITH 100nF CAPACITOR 400 200 250 300 350 SAMPLE NUMBER 400 450 500 550 300 REFOUT = 2.
Data Sheet AD5382 FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL The AD5382 is a complete, single-supply, 32-channel voltage output DAC that offers 14-bit resolution. The part is available in a 100-lead LQFP package and features both a parallel and a serial interface. This product includes an internal, softwareselectable, 1.25 V/2.5 V, 10 ppm/°C reference, which can be used to drive the buffered reference inputs; alternatively, an external reference can be used to drive these inputs.
AD5382 Data Sheet Soft Clear Table 13. Gain Data Format (REG1 = 0, REG0 = 1) 11 10 01 00 00 DB13 to DB0 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 Gain Factor 1 0.75 0.5 0.25 0 1110 1110 1110 1110 0000 REG1 = REG0 = 0, A4–A0 = 00010 DB13–DB0 = Don’t Care Executing this instruction performs a software clear, which is functionally the same as that provided by the external CLR pin. The DAC outputs are loaded with the data in the Clear Code. register (Table 14).
Data Sheet AD5382 Table 15. Control Register Contents MSB CR13 CR12 CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 LSB CR0 Control Register Write/Read REG1 = REG0 = 0, A4–A0 = 01100, R/W status determines if the operation is a write (R/W = 0) or a read (R/W = 1). DB13 to DB0 contain the control register data. Control Register Contents CR13: Power-Down Status. This bit is used to configure the output amplifier state in power-down. CR13 = 1.
AD5382 Data Sheet Table 17.
Data Sheet AD5382 HARDWARE FUNCTIONS RESET FUNCTION FIFO OPERATION IN PARALLEL MODE Bringing the RESET line low resets the contents of all internal registers to their power-on reset state. Reset is a negative edgesensitive input. The default corresponds to m at full scale and to c at zero scale. The contents of the DAC registers are cleared, setting VOUT0 to VOUT31 to 0 V. This sequence takes 270 µs max.
AD5382 Data Sheet AD5382 INTERFACES Figure 3 and Figure 5 show timing diagrams for a serial write to the AD5382 in standalone and daisy-chain modes. The 24-bit data-word format for the serial interface is shown in Table 18. The AD5382 contains both parallel and serial interfaces. Furthermore, the serial interface can be programmed to be either SPI-, DSP-, MICROWIRE-, or I2C-compatible. The SER/PAR pin selects parallel and serial interface modes.
Data Sheet AD5382 Daisy-Chain Mode Readback Mode For systems that contain several devices, the SDO pin can be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. Readback mode is invoked by setting the R/W bit = 1 in the serial input register write. With R/W = 1, Bits A4 to A0, in association with Bits REG1 and REG0, select the register to be read.
AD5382 Data Sheet I2C SERIAL INTERFACE The AD5382 features an I2C-compatible 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the AD5382 and the master at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing diagrams that incorporate three different modes of operation.
Data Sheet AD5382 SCL 1 SDA 0 1 0 1 AD1 AD0 START COND BY MASTER R/W 0 ACK BY AD538x MSB 0 0 A4 A3 A2 A1 A0 ACK BY AD538x ADDRESS BYTE POINTER BYTE SCL REG1 REG0 MSB LSB MSB LSB ACK BY AD538x ACK BY AD538x MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE STOP COND BY MASTER 03733-031 SDA Figure 30.
AD5382 Data Sheet 2-Byte Mode Following initialization of 2-byte mode, the user can update channels sequentially. The device address byte is required only once, and the pointer address pointer is configured for autoincrement or burst mode. PARALLEL INTERFACE The SER/PAR pin must be tied low to enable the parallel interface and disable the serial interfaces. Figure 7 shows the timing diagram for a parallel write. The parallel interface is controlled by the following pins.
Data Sheet AD5382 MICROPROCESSOR INTERFACING The AD5382 can be interfaced to a variety of 16-bit microcontrollers or DSP processors. Figure 34 shows the AD5382 family interfaced to a generic 16-bit microcontroller/DSP processor. The lower address lines from the processor are connected to A0–A4 on the AD5382. The upper address lines are decoded to provide a CS, LDAC signal for the AD5382.
AD5382 Data Sheet AD5382 to PIC16C6x/7x RESET SDO SDO/RC5 DIN SCK/RC3 SCLK RA1 SYNC PINS OMITTED FOR CLARITY. 03733-036 SPI/I2C 1ADDITIONAL RESET SDO RxD DIN TxD SCLK P1.1 SYNC SPI/I2C 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 36. AD5382-to-8051 Interface AD5382 to ADSP-2101/ADSP-2103 AD53821 SER/PAR SDI/RC4 SER/PAR Figure 35. AD5382-to-PIC16C6x/7x Interface Figure 37 shows a serial interface between the AD5382 and the ADSP-2101/ADSP-2103.
Data Sheet AD5382 APPLICATION INFORMATION POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5382 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board.
AD5382 Data Sheet MONITOR FUNCTION The AD5382 channel monitor function consists of a multiplexer addressed via the interface, allowing any channel output to be routed to this pin for monitoring using an external ADC. The channel monitor function must be enabled in the control register before any channels are routed to MON_OUT. Table 17 contains the decoding information required to route any channel to MON_OUT.
Data Sheet AD5382 DATA REGISTER A DAC REGISTER 14-BIT DAC VOUT LDAC CONTROL INPUT A/B 03733-042 DATA REGISTER B INPUT INPUT DATA REGISTER Figure 41. Toggle Mode Function +5V 0.01µF REFOUT/REFIN OUTPUT RANGE 0V TO 200V AVDD VOUT1 14-BIT DAC ACTUATORS FOR MEMS MIRROR ARRAY G = 50 14-BIT DAC VOUT31 SENSOR AND MULTIPLEXER 8-CHANNEL ADC (AD7856) OR SINGLE CHANNEL ADC (AD7671) G = 50 ADSP-21065L 03733-043 AD5382 Figure 42.
AD5382 Data Sheet OPTICAL ATTENUATORS The AD5382 controls the optical attenuator for each wavelength, ensuring that the power is equalized in all wavelengths before being multiplexed onto the fiber. This prevents information loss and saturation from occurring at amplification stages further along the fiber.
Data Sheet AD5382 OUTLINE DIMENSIONS 16.20 16.00 SQ 15.80 1.60 MAX 0.75 0.60 0.45 100 1 76 75 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY 51 50 25 26 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW 0.27 0.22 0.17 051706-A 1.45 1.40 1.35 COMPLIANT TO JEDEC STANDARDS MS-026-BED Figure 44.
AD5382 Data Sheet NOTES Rev.
Data Sheet AD5382 NOTES Rev.
AD5382 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). © 2004–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03733-0-10/12(C) Rev.