Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - DA converter (DAC) LQFP 100

Data Sheet AD5381

Rev. D | Page 21 of 40

FUNCTIONAL DESCRIPTION

DAC ARCHITECTURE—GENERAL

The AD5381 is a complete, single-supply, 40-channel voltage

output DAC that offers 12-bit resolution. The part is available

in a 100-lead LQFP package and features both a parallel and

a serial interface. This product includes an internal, software

selectable, 1.25 V/2.5 V, 1 0 ppm/°C reference that can be used

to drive the buffered reference inputs; alternatively, an external

reference can be used to drive these inputs. Internal/external

reference selection is via the CR8 bit in the control register;

CR10 selects the reference magnitude if the internal reference

is selected. All channels have an on-chip output amplifier with

rail-to-rail output capable of driving 5 kΩ in parallel with a

200 pF load.

03732-027

VOUT

12-BIT

DAC

REG

m REG

c REG

×1 INPUT

REG

×2INPUT DATA

VREF AVDD

Figure 27. Single-Channel Architecture

The architecture of a single DAC channel consists of a 12-bit

resistor-string DAC followed by an output buffer amplifier

operating at a gain of 2. This resistor-string architecture

guarantees DAC monotonicity. The 12-bit binary digital code

loaded to the DAC register determines at what node on the

string the voltage is tapped off before being fed to the output

amplifier. Each channel on these devices contains independent

offset and gain control registers that allow the user to digitally

trim offset and gain. These registers give the user the ability to

calibrate out errors in the complete signal chain, including the

DAC, using the internal m and c registers, which hold the

correction factors. All channels are double buffered, allow-

ing synchronous updating of all channels using the

LDAC

pin.

Figure 27 shows a block diagram of a single channel on the

AD5381. The digital input transfer function for each DAC

can be represented as

x2 = [(m + 2)/ 2

× x1] + (c – 2

n – 1

)

where:

x2 = the data-word loaded to the resistor string DAC.

x1 = the 12-bit data-word written to the DAC input register.

m = the gain coefficient (default is 0xFFE). The gain coefficient

is written to the 11 most significant bits (DB11 to DB1), the LSB

(DB0) of the data-word is a 0.

n = DAC resolution (n = 12 for AD5381).

c = the12-bit offset coefficient (default is 0x800).

The complete transfer function for these devices can be

represented as

VOUT = 2 × V

REF

× x2/2

where:

x2 is the data-word loaded to the resistor string DAC. V

REF

is externally applied to the DAC REFOUT/REFIN pin. For

specified performance, an external reference voltage of 2.5 V is

recommended for the AD5381-5, and 1.25 V for the AD5381-3.

DATA DECODING

The AD5381 contains a 12-bit data bus, DB11 to DB0. Depend-

ing on the value of REG1 and REG0 (see Table 10), this data is

loaded into the addressed DAC input registers, offset (c)

registers, or gain (m) registers. The format data, offset (c), and

gain (m) register contents are shown in Table 11 to Table 13.

Table 10. Register Selection

REG1 REG0 Register Selected

1 1 Input Data Register (x1)

1 0 Offset Register (c)

0 1 Gain Register (m)

0 0 Special Function Registers (SFRs)

Table 11. DAC Data Format (REG1 = 1, REG0 = 1)

DB11 to DB0 DAC Output (V)

1111 1111 1111 2 V

REF

× (4095/4096)

1111 1111 1110 2 V

REF

× (4094/4096)

1000 0000 0001 2 V

REF

× (2049/4096)

1000 0000 0000 2 V

REF

× (2048/4096)

0111 1111 1111 2 V

REF

× (2047/4096)

0000 0000 0001 2 V

REF

× (1/4096)

0000

Table 12. Offset Data Format (REG1 = 1, REG0 = 0)

DB11 to DB0 Offset (LSB)

1111 1111 1111 +2048

1111 1111 1110 +2047

1000 0000 0001 +1

1000 0000 0000 0

0111

1111

–1

0000 0000 0001 –2047

0000

–2048

Table 13. Gain Data Format (REG1 = 0, REG0 = 1)

DB11 to DB0 Gain Factor

1111 1111 1110 1

1011 1111 1110 0.75

0111 1111 1110 0.5

0011

1111

1110

0.25

0000