AD5381 Data Sheet
Rev. D | Page 12 of 40
t
18
t
18
t
19
t
20
t
13
t
3
t
2
t
8
t
13
t
11
t
9
t
12
t
0
t
1
t
15
t
7
t
6
t
17
t
16
t
10
t
14
t
4
t
5
REG0, REG1, A5...A0
CS
WR
DB11...DB0
BUSY
LDAC
1
VOUT1
VOUT2
CLR
VOUT
LDAC
2
1
LDAC ACTIVE DURING BUSY.
2
LDAC ACTIVE AFTER BUSY.
03732-007
Figure 7. Parallel Interface Timing Diagram
