Datasheet

AD5381 Data Sheet
Rev. D | Page 10 of 40
I
2
C SERIAL INTERFACE TIMING
DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T
MIN
to T
MAX
,
unless otherwise noted.
Table 6.
Parameter
1, 2
Limit at T
MIN
, T
MAX
Unit Description
F
SCL
400 kHz max SCL clock frequency
t
1
2.5 µs min SCL cycle time
t
2
0.6
µs min
t
HIGH
, SCL high time
t
3
1.3 µs min t
LOW
, SCL low time
t
4
0.6
µs min
t
HD,STA
, start/repeated start condition hold time
t
5
100
ns min
t
SU,DAT
, data setup time
t
6
3
0.9 µs max t
HD,DAT
, data hold time
0 µs min t
HD,DAT
, data hold time
t
7
0.6 µs min t
SU,STA
, setup time for repeated start
t
8
0.6 µs min t
SU,STO
, stop condition setup time
t
9
1.3 µs min t
BUF
, bus free time between a STOP and a START condition
t
10
300 ns max t
R
, rise time of SCL and SDA when receiving
0 ns min t
R
, rise time of SCL and SDA when receiving (CMOS compatible)
t
11
300 ns max t
F
, fall time of SDA when transmitting
0 ns min t
F
, fall time of SDA when receiving (CMOS compatible)
300 ns max t
F
, fall time of SCL and SDA when receiving
20 + 0.1 C
b
4
ns min t
F
, fall time of SCL and SDA when transmitting
C
b
400 pF max Capacitive load for each bus line
1
Guaranteed by design and characterization, not production tested.
2
See Figure 6.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
4
C
b
is the total capacitance, in pF, of one bus line. t
R
and t
F
are measured between 0.3 DVDD and 0.7 DVDD.
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t
9
t
3
t
1
t
11
t
4
t
10
t
4
t
5
t
7
t
6
t
8
t
2
SDA
SCL
03732-006
Figure 6. I
2
C-Compatible Serial Interface Timing Diagram